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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DCACHE.v
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// Filename: DCACHE.v
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// Version: 1.0
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// Version: 1.1 bug fix
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 7 October 2015
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2015 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// Modules contained in this file:
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// Modules contained in this file:
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// DCACHE the data cache of M32632
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// DCACHE the data cache of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DCACHE( BCLK, MCLK, WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW,
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module DCACHE( BCLK, MCLK, WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, QWATWO,
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WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
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WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
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PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
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PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
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ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
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ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
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RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
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RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
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input PSR_USER;
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input PSR_USER;
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input WRITE;
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input WRITE;
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input READ;
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input READ;
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input ZTEST;
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input ZTEST;
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input RMW;
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input RMW;
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input QWATWO;
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input WAMUX;
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input WAMUX;
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input ENWR;
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input ENWR;
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input IC_PREQ;
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input IC_PREQ;
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input FILLRAM;
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input FILLRAM;
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input [1:0] CFG;
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input [1:0] CFG;
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assign DAT_SET = WRITE ? WRDATA : DRAM_Q ;
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assign DAT_SET = WRITE ? WRDATA : DRAM_Q ;
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assign BE_SET = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
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assign BE_SET = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
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assign ADDR = KOMUX ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
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assign ADDR = KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
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assign A_SET = WAMUX ? WADDR : VADR_R[11:2] ;
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assign A_SET = WAMUX ? WADDR : VADR_R[11:2] ;
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assign TAGA = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
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assign TAGA = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
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.CA_HIT(CA_HIT),
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.CA_HIT(CA_HIT),
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.READ(READ),
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.READ(READ),
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.WRITE(WRITE),
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.WRITE(WRITE),
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.ZTEST(ZTEST),
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.ZTEST(ZTEST),
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.RMW(RMW),
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.RMW(RMW),
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.QWATWO(QWATWO),
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.USE_CA(USE_CA),
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.USE_CA(USE_CA),
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.PTB_WR(PTB_WR),
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.PTB_WR(PTB_WR),
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.PTB_SEL(PTB_SEL),
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.PTB_SEL(PTB_SEL),
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.SEL_PTB1(SEL_PTB1),
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.SEL_PTB1(SEL_PTB1),
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.IO_READY(IO_READY),
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.IO_READY(IO_READY),
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