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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DCACHE.v
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// Filename: DCACHE.v
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// Version: 1.1 bug fix
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// Version: 2.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.1 bug fix of 7 October 2015
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// Date: 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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// Modules contained in this file:
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// Modules contained in this file:
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// DCACHE the data cache of M32632
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// DCACHE the data cache of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DCACHE( BCLK, MCLK, WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, QWATWO,
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module DCACHE( BCLK, MCLK, WRCFG, DRAMSZ, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW,
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WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
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QWATWO, WAMUX, ENWR, IC_PREQ, DMA_CHK, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR,
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PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
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MCR_FLAGS, PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET,
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ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
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HLDA, ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
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RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
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RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
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input BCLK;
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input BCLK;
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input MCLK;
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input MCLK;
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input WRCFG;
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input WRCFG;
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input [2:0] DRAMSZ;
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input MDONE;
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input MDONE;
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input BRESET;
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input BRESET;
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input PTB_WR;
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input PTB_WR;
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input PTB_SEL;
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input PTB_SEL;
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input IO_READY;
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input IO_READY;
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| Line 60... |
Line 62... |
input RMW;
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input RMW;
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input QWATWO;
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input QWATWO;
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input WAMUX;
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input WAMUX;
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input ENWR;
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input ENWR;
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input IC_PREQ;
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input IC_PREQ;
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input FILLRAM;
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input DMA_CHK;
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input [1:0] CFG;
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input [1:0] CFG;
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input [1:0] CINVAL;
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input [1:0] CINVAL;
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input [27:4] DMA_AA;
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input [27:4] DMA_AA;
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input [63:0] DP_Q;
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input [63:0] DP_Q;
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input [31:0] DRAM_Q;
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input [31:0] DRAM_Q;
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Line 189... |
reg [15:0] TAG0;
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reg [15:0] TAG0;
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reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [15:0] TAG1;
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reg [15:0] TAG1;
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reg [23:0] CA_VALID [0:31]; // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
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wire [23:0] CVALID;
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reg [23:0] CVALID;
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_Q;
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reg [35:0] MMU_Q;
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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| Line 258... |
Line 259... |
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always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
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always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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always @(posedge BCLK) CVALID <= CA_VALID[TAGA[11:7]];
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NEU_VALID VALID_RAM(
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.BCLK(BCLK),
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always @(negedge BCLK) if (WE_CV) CA_VALID[WADR_CV] <= DAT_CV;
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.VALIN(DAT_CV),
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.WADR(WADR_CV),
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.WREN(WE_CV),
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.RADR(TAGA[11:7]),
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.VALOUT(CVALID) );
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
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always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
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.WB_ACC(WB_ACC),
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.WB_ACC(WB_ACC),
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.ADR_EQU(ADR_EQU),
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.ADR_EQU(ADR_EQU),
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.IC_PREQ(IC_PREQ),
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.IC_PREQ(IC_PREQ),
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.CAPDAT(CAPDAT[31:0]),
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.CAPDAT(CAPDAT[31:0]),
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.CPU_OUT(DP_Q[59:44]),
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.CPU_OUT(DP_Q[59:44]),
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.FILLRAM(FILLRAM),
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.DMA_CHK(DMA_CHK),
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.IC_VA(IC_VA),
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.IC_VA(IC_VA),
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.ICTODC(ICTODC),
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.ICTODC(ICTODC),
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.VADR_R(VADR_R[31:12]),
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.VADR_R(VADR_R[31:12]),
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.NEW_PTB(NEW_PTB),
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.NEW_PTB(NEW_PTB),
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.PTB_ONE(PTB_ONE),
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.PTB_ONE(PTB_ONE),
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Line 384... |
.INVAL_L(CINVAL[0]),
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.INVAL_L(CINVAL[0]),
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.CI(CI),
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.CI(CI),
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.MMU_HIT(MMU_HIT),
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.MMU_HIT(MMU_HIT),
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.WRITE(WRITE),
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.WRITE(WRITE),
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.KDET(KDET),
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.KDET(KDET),
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.ADDR(ADDR),
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.ADDR({RADR[31:28],ADDR}),
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.CFG(CFG),
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.CFG(CFG),
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.ENDRAM(ENDRAM),
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.ENDRAM(ENDRAM),
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.CVALID(CVALID),
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.CVALID(CVALID),
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.TAG0(TAG0),
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.TAG0(TAG0),
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.TAG1(TAG1),
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.TAG1(TAG1),
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.CA_HIT(CA_HIT),
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.CA_HIT(CA_HIT),
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.CA_SET(CA_SET),
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.CA_SET(CA_SET),
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.WB_ACC(WB_ACC),
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.WB_ACC(WB_ACC),
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.USE_CA(USE_CA),
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.USE_CA(USE_CA),
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.IOSEL(RADR[31:28]),
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.DRAMSZ(DRAMSZ),
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.IO_SPACE(IO_SPACE),
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.IO_SPACE(IO_SPACE),
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.KILL(KILL),
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.KILL(KILL),
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.DC_ILO(RWVAL[2]),
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.DC_ILO(RWVAL[2]),
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.UPDATE(UPDATE_C));
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.UPDATE(UPDATE_C));
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