| Line 1... |
Line 1... |
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DCACHE.v
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// Filename: DCACHE.v
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// Version: 2.0
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// Version: 3.0 Cache Interface reworked
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// History: 1.1 bug fix of 7 October 2015
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// History: 2.1 bug fix of November 2016
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// 2.0 50 MHz release of 14 August 2016
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// 1.1 bug fix of 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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// Date: 2 December 2018
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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| Line 30... |
Line 32... |
//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// DCACHE the data cache of M32632
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// DCACHE the data cache of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DCACHE( BCLK, MCLK, WRCFG, DRAMSZ, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW,
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module DCACHE( BCLK, DRAMSZ, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, CTRL_QW, PSR_USER, WRITE, READ, RMW,
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QWATWO, WAMUX, ENWR, IC_PREQ, DMA_CHK, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR,
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QWATWO, ENWR, IC_PREQ, DMA_CHK, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR,
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MCR_FLAGS, PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET,
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MCR_FLAGS, PACKET, SIZE, VADR, INHIBIT, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET,
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HLDA, ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
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HLDA, ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
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RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
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RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
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input BCLK;
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input BCLK;
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input MCLK;
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input WRCFG;
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input [2:0] DRAMSZ;
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input [2:0] DRAMSZ;
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input MDONE;
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input MDONE;
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input BRESET;
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input BRESET;
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input PTB_WR;
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input PTB_WR;
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input PTB_SEL;
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input PTB_SEL;
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input IO_READY;
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input IO_READY;
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input REG_OUT;
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input [1:0] CTRL_QW;
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input PSR_USER;
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input PSR_USER;
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input WRITE;
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input WRITE;
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input READ;
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input READ;
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input ZTEST;
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input ZTEST;
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input RMW;
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input RMW;
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input QWATWO;
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input QWATWO;
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input WAMUX;
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input ENWR;
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input ENWR;
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input IC_PREQ;
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input IC_PREQ;
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input DMA_CHK;
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input DMA_CHK;
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input [1:0] CFG;
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input [1:0] CFG;
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input [1:0] CINVAL;
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input [1:0] CINVAL;
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input [27:4] DMA_AA;
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input [28:4] DMA_AA;
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input [63:0] DP_Q;
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input [63:0] DP_Q;
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input [31:0] DRAM_Q;
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input [127:0] DRAM_Q;
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input [31:12] IC_VA;
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input [31:12] IC_VA;
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input [3:0] ICTODC;
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input [3:0] ICTODC;
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input [31:0] IO_Q;
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input [31:0] IO_Q;
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input [1:0] IVAR;
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input [1:0] IVAR;
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input [3:0] MCR_FLAGS;
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input [3:0] MCR_FLAGS;
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input [3:0] PACKET;
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input [3:0] PACKET;
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input [1:0] SIZE;
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input [1:0] SIZE;
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input [31:0] VADR;
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input [31:0] VADR;
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input [11:2] WADDR;
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input INHIBIT;
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input [2:0] WCTRL;
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input [2:0] RWVAL;
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input [2:0] RWVAL;
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input [40:2] DBG_IN;
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input [40:2] DBG_IN;
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input ENDRAM;
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input ENDRAM;
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output IO_RD;
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output IO_RD;
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| Line 95... |
Line 93... |
output RWVFLAG;
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output RWVFLAG;
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output [5:0] ACC_STAT;
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output [5:0] ACC_STAT;
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output [31:0] DP_DI;
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output [31:0] DP_DI;
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output [3:1] IACC_STAT;
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output [3:1] IACC_STAT;
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output [1:0] IC_SIGS;
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output [1:0] IC_SIGS;
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output [27:4] KOLLI_A;
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output [28:4] KOLLI_A;
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output [23:0] MMU_DIN;
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output [23:0] MMU_DIN;
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output reg [27:0] DRAM_A;
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output reg [28:0] DRAM_A;
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output reg [35:0] DRAM_DI;
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output reg [35:0] DRAM_DI;
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output reg [31:0] IO_A;
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output reg [31:0] IO_A;
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output reg [3:0] IO_BE;
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output reg [3:0] IO_BE;
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output reg [31:0] IO_DI;
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output reg [31:0] IO_DI;
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output DBG_HIT;
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output DBG_HIT;
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| Line 109... |
Line 107... |
reg [31:0] DFFE_IOR;
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reg [31:0] DFFE_IOR;
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reg [31:0] CAPDAT;
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reg [31:0] CAPDAT;
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reg [31:0] VADR_R;
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reg [31:0] VADR_R;
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reg AUX_ALT;
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reg AUX_ALT;
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reg DFF_QWEXT;
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reg DFF_QWEXT;
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reg [11:4] KOLLI_AR;
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wire [27:4] ADDR;
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wire [28:4] ADDR;
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wire ADR_EQU;
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wire ADR_EQU;
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wire AUX_DAT;
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wire AUX_DAT;
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wire CA_HIT;
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wire CA_HIT;
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wire CA_SET;
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wire CA_SET;
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wire CUPDATE;
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wire CUPDATE;
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| Line 126... |
Line 125... |
wire IO_SPACE;
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wire IO_SPACE;
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wire KOMUX;
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wire KOMUX;
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wire MMU_HIT;
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wire MMU_HIT;
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wire NEW_PTB;
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wire NEW_PTB;
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wire PTB_ONE;
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wire PTB_ONE;
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wire [27:0] PTE_ADR;
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wire [28:0] PTE_ADR;
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wire [31:12] RADR;
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wire [31:12] RADR;
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wire [11:4] TAGA;
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wire [11:4] TAGA;
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wire [23:0] UPDATE_C;
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wire [23:0] UPDATE_C;
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wire [31:0] UPDATE_M;
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wire [31:0] UPDATE_M;
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wire USE_CA;
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wire USE_CA;
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| Line 143... |
Line 142... |
wire PTE_MUX;
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wire PTE_MUX;
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wire WE_CV;
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wire WE_CV;
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wire [23:0] DAT_CV;
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wire [23:0] DAT_CV;
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wire [4:0] WADR_CV;
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wire [4:0] WADR_CV;
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wire WRSET0;
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wire WRSET0;
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wire [3:0] BE_SET;
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wire [15:0] BE_SET;
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wire [31:0] DAT_SET;
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wire [127:0] DAT_SET;
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wire [9:0] A_SET;
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wire [31:0] CAP_Q;
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wire WRSET1;
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wire WRSET1;
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wire SEL_PTB1;
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wire SEL_PTB1;
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wire CI;
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wire CI;
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wire [27:0] ADR_MX;
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wire [28:0] ADR_MX;
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wire LD_DRAM_A;
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wire LD_DRAM_A;
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wire VIRTUELL;
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wire VIRTUELL;
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wire NEW_PTB_RUN;
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wire NEW_PTB_RUN;
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wire KILL;
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wire KILL;
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wire LAST_MUX;
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wire LAST_MUX;
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| Line 168... |
Line 167... |
wire PROT_ERROR;
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wire PROT_ERROR;
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wire AUX_QW;
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wire AUX_QW;
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wire PD_MUX;
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wire PD_MUX;
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wire [19:0] PTE_DAT;
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wire [19:0] PTE_DAT;
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wire PKEEP;
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wire PKEEP;
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wire XADDR2;
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wire [28:12] TAGDAT;
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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reg [7:0] DATA0_D [0:1023]; // Data Set 0 : 4 kBytes
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reg [7:0] DATA0_P [0:255]; // Data Set 0 : 4 kBytes
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reg [7:0] DATA0_C [0:1023];
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reg [7:0] DATA0_O [0:255];
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reg [7:0] DATA0_B [0:1023];
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reg [7:0] DATA0_N [0:255];
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reg [7:0] DATA0_A [0:1023];
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reg [7:0] DATA0_M [0:255];
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reg [7:0] DATA0_L [0:255]; // Data Set 0 : 4 kBytes
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reg [7:0] DATA0_K [0:255];
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reg [7:0] DATA0_J [0:255];
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reg [7:0] DATA0_I [0:255];
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reg [7:0] DATA0_H [0:255]; // Data Set 0 : 4 kBytes
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reg [7:0] DATA0_G [0:255];
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reg [7:0] DATA0_F [0:255];
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reg [7:0] DATA0_E [0:255];
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reg [7:0] DATA0_D [0:255]; // Data Set 0 : 4 kBytes
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reg [7:0] DATA0_C [0:255];
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reg [7:0] DATA0_B [0:255];
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reg [7:0] DATA0_A [0:255];
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reg [127:0] RDDATA0;
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reg [31:0] SET_DAT0;
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reg [31:0] SET_DAT0;
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reg [7:0] DATA1_D [0:1023]; // Data Set 1 : 4 kBytes
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reg [7:0] DATA1_P [0:255]; // Data Set 1 : 4 kBytes
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reg [7:0] DATA1_C [0:1023];
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reg [7:0] DATA1_O [0:255];
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reg [7:0] DATA1_B [0:1023];
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reg [7:0] DATA1_N [0:255];
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reg [7:0] DATA1_A [0:1023];
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reg [7:0] DATA1_M [0:255];
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reg [7:0] DATA1_L [0:255]; // Data Set 1 : 4 kBytes
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reg [7:0] DATA1_K [0:255];
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reg [7:0] DATA1_J [0:255];
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reg [7:0] DATA1_I [0:255];
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reg [7:0] DATA1_H [0:255]; // Data Set 1 : 4 kBytes
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reg [7:0] DATA1_G [0:255];
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reg [7:0] DATA1_F [0:255];
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reg [7:0] DATA1_E [0:255];
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reg [7:0] DATA1_D [0:255]; // Data Set 1 : 4 kBytes
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reg [7:0] DATA1_C [0:255];
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reg [7:0] DATA1_B [0:255];
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reg [7:0] DATA1_A [0:255];
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reg [127:0] RDDATA1;
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reg [31:0] SET_DAT1;
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reg [31:0] SET_DAT1;
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reg [15:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 16 bits
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reg [16:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 17 bits
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reg [15:0] TAG0;
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reg [16:0] TAG0;
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reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [16:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 17 bits
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reg [15:0] TAG1;
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reg [16:0] TAG1;
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wire [23:0] CVALID;
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wire [23:0] CVALID;
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_Q;
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reg [35:0] MMU_Q;
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MVALID;
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reg [31:0] MVALID;
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assign ADR_EQU = ({RADR[27:12],VADR_R[11:4]} == DRAM_A[27:4]); // Limited to 256 MB
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assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
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assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
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assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
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assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
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assign ADR_MX = PTE_MUX ? PTE_ADR : {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET} ;
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assign ADR_MX = PTE_MUX ? PTE_ADR : {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET} ;
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assign KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[27:4] ;
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assign KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[28:4] ;
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assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
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assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
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assign VIRT_A = ~CINVAL[0] & VIRTUELL;
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assign VIRT_A = ~CINVAL[0] & VIRTUELL;
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assign USER = ~MCR_FLAGS[3] & PSR_USER;
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assign USER = ~MCR_FLAGS[3] & PSR_USER;
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assign DAT_SET = WRITE ? WRDATA : DRAM_Q ;
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assign ADDR = KDET ? {KOLLI_A[28:12],KOLLI_AR} : {RADR[28:12],VADR_R[11:4]} ;
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assign BE_SET = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
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assign ADDR = KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
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assign A_SET = WAMUX ? WADDR : VADR_R[11:2] ;
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assign TAGA = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
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assign TAGA = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
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assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
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assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
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| Line 234... |
Line 253... |
assign LD_DRAM_A = ~(DRAM_ACC | PKEEP);
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assign LD_DRAM_A = ~(DRAM_ACC | PKEEP);
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|
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assign ACC_STAT[4] = IO_ACC;
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assign ACC_STAT[4] = IO_ACC;
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assign ACC_STAT[5] = CA_HIT;
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assign ACC_STAT[5] = CA_HIT;
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|
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assign XADDR2 = VADR_R[2] ^ CTRL_QW[1];
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|
|
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always @(posedge BCLK) KOLLI_AR <= KOLLI_A[11:4];
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|
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (IO_ACC)
|
if (IO_ACC)
|
begin
|
begin
|
IO_BE <= ENBYTE;
|
IO_BE <= ENBYTE;
|
IO_DI <= WRDATA;
|
IO_DI <= WRDATA;
|
IO_A <= {RADR[31:12],VADR_R[11:0]};
|
IO_A <= {RADR[31:12],VADR_R[11:3],XADDR2,VADR_R[1:0]};
|
end
|
end
|
|
|
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= ADR_MX[27:0];
|
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[28:0] <= ADR_MX[28:0];
|
|
|
always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
|
always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
|
|
|
always @(posedge BCLK)
|
always @(posedge BCLK)
|
begin
|
begin
|
| Line 255... |
Line 278... |
AUX_ALT <= DFF_QWEXT | IO_RD;
|
AUX_ALT <= DFF_QWEXT | IO_RD;
|
DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
|
DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
|
VADR_R <= VADR;
|
VADR_R <= VADR;
|
end
|
end
|
|
|
always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
|
always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
|
|
|
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
|
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
|
|
|
NEU_VALID VALID_RAM(
|
NEU_VALID VALID_RAM(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
| Line 271... |
Line 294... |
|
|
// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
|
// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
|
|
|
always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
|
always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
|
|
|
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
|
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;
|
|
|
// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
|
// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
|
|
|
always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];
|
always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];
|
|
|
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
|
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;
|
|
|
|
// +++++++++++++++++++++++++ DIN MUX +++++++++++++++++++++++
|
|
|
|
WRPORT DINMUX(
|
|
.WRITE(WRITE),
|
|
.DRAM_Q(DRAM_Q),
|
|
.DADDR(DRAM_A[3:2]),
|
|
.VADDR(VADR_R[3:2]),
|
|
.WRDATA(WRDATA),
|
|
.ENBYTE(ENBYTE),
|
|
.CAP_Q(CAP_Q),
|
|
.WDAT(DAT_SET),
|
|
.ENB(BE_SET) );
|
|
|
// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
|
// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
|
|
|
always @(posedge BCLK)
|
always @(posedge BCLK)
|
begin
|
begin
|
SET_DAT0[31:24] <= DATA0_D[VADR[11:2]];
|
RDDATA0[127:120] <= DATA0_P[VADR[11:4]];
|
SET_DAT0[23:16] <= DATA0_C[VADR[11:2]];
|
RDDATA0[119:112] <= DATA0_O[VADR[11:4]];
|
SET_DAT0[15:8] <= DATA0_B[VADR[11:2]];
|
RDDATA0[111:104] <= DATA0_N[VADR[11:4]];
|
SET_DAT0[7:0] <= DATA0_A[VADR[11:2]];
|
RDDATA0[103:96] <= DATA0_M[VADR[11:4]];
|
|
RDDATA0[95:88] <= DATA0_L[VADR[11:4]];
|
|
RDDATA0[87:80] <= DATA0_K[VADR[11:4]];
|
|
RDDATA0[79:72] <= DATA0_J[VADR[11:4]];
|
|
RDDATA0[71:64] <= DATA0_I[VADR[11:4]];
|
|
RDDATA0[63:56] <= DATA0_H[VADR[11:4]];
|
|
RDDATA0[55:48] <= DATA0_G[VADR[11:4]];
|
|
RDDATA0[47:40] <= DATA0_F[VADR[11:4]];
|
|
RDDATA0[39:32] <= DATA0_E[VADR[11:4]];
|
|
RDDATA0[31:24] <= DATA0_D[VADR[11:4]];
|
|
RDDATA0[23:16] <= DATA0_C[VADR[11:4]];
|
|
RDDATA0[15:8] <= DATA0_B[VADR[11:4]];
|
|
RDDATA0[7:0] <= DATA0_A[VADR[11:4]];
|
end
|
end
|
|
|
always @(posedge MCLK)
|
always @(RDDATA0 or VADR_R)
|
|
case (VADR_R[3:2])
|
|
2'b00 : SET_DAT0 <= RDDATA0[31:0];
|
|
2'b01 : SET_DAT0 <= RDDATA0[63:32];
|
|
2'b10 : SET_DAT0 <= RDDATA0[95:64];
|
|
2'b11 : SET_DAT0 <= RDDATA0[127:96];
|
|
endcase
|
|
|
|
always @(posedge BCLK)
|
if (WRSET0)
|
if (WRSET0)
|
begin
|
begin
|
if (BE_SET[3]) DATA0_D[A_SET] <= DAT_SET[31:24];
|
if (BE_SET[15]) DATA0_P[VADR_R[11:4]] <= DAT_SET[127:120];
|
if (BE_SET[2]) DATA0_C[A_SET] <= DAT_SET[23:16];
|
if (BE_SET[14]) DATA0_O[VADR_R[11:4]] <= DAT_SET[119:112];
|
if (BE_SET[1]) DATA0_B[A_SET] <= DAT_SET[15:8];
|
if (BE_SET[13]) DATA0_N[VADR_R[11:4]] <= DAT_SET[111:104];
|
if (BE_SET[0]) DATA0_A[A_SET] <= DAT_SET[7:0];
|
if (BE_SET[12]) DATA0_M[VADR_R[11:4]] <= DAT_SET[103:96];
|
|
if (BE_SET[11]) DATA0_L[VADR_R[11:4]] <= DAT_SET[95:88];
|
|
if (BE_SET[10]) DATA0_K[VADR_R[11:4]] <= DAT_SET[87:80];
|
|
if (BE_SET[9]) DATA0_J[VADR_R[11:4]] <= DAT_SET[79:72];
|
|
if (BE_SET[8]) DATA0_I[VADR_R[11:4]] <= DAT_SET[71:64];
|
|
if (BE_SET[7]) DATA0_H[VADR_R[11:4]] <= DAT_SET[63:56];
|
|
if (BE_SET[6]) DATA0_G[VADR_R[11:4]] <= DAT_SET[55:48];
|
|
if (BE_SET[5]) DATA0_F[VADR_R[11:4]] <= DAT_SET[47:40];
|
|
if (BE_SET[4]) DATA0_E[VADR_R[11:4]] <= DAT_SET[39:32];
|
|
if (BE_SET[3]) DATA0_D[VADR_R[11:4]] <= DAT_SET[31:24];
|
|
if (BE_SET[2]) DATA0_C[VADR_R[11:4]] <= DAT_SET[23:16];
|
|
if (BE_SET[1]) DATA0_B[VADR_R[11:4]] <= DAT_SET[15:8];
|
|
if (BE_SET[0]) DATA0_A[VADR_R[11:4]] <= DAT_SET[7:0];
|
end
|
end
|
|
|
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
|
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
|
|
|
always @(posedge BCLK)
|
always @(posedge BCLK)
|
begin
|
begin
|
SET_DAT1[31:24] <= DATA1_D[VADR[11:2]];
|
RDDATA1[127:120] <= DATA1_P[VADR[11:4]];
|
SET_DAT1[23:16] <= DATA1_C[VADR[11:2]];
|
RDDATA1[119:112] <= DATA1_O[VADR[11:4]];
|
SET_DAT1[15:8] <= DATA1_B[VADR[11:2]];
|
RDDATA1[111:104] <= DATA1_N[VADR[11:4]];
|
SET_DAT1[7:0] <= DATA1_A[VADR[11:2]];
|
RDDATA1[103:96] <= DATA1_M[VADR[11:4]];
|
|
RDDATA1[95:88] <= DATA1_L[VADR[11:4]];
|
|
RDDATA1[87:80] <= DATA1_K[VADR[11:4]];
|
|
RDDATA1[79:72] <= DATA1_J[VADR[11:4]];
|
|
RDDATA1[71:64] <= DATA1_I[VADR[11:4]];
|
|
RDDATA1[63:56] <= DATA1_H[VADR[11:4]];
|
|
RDDATA1[55:48] <= DATA1_G[VADR[11:4]];
|
|
RDDATA1[47:40] <= DATA1_F[VADR[11:4]];
|
|
RDDATA1[39:32] <= DATA1_E[VADR[11:4]];
|
|
RDDATA1[31:24] <= DATA1_D[VADR[11:4]];
|
|
RDDATA1[23:16] <= DATA1_C[VADR[11:4]];
|
|
RDDATA1[15:8] <= DATA1_B[VADR[11:4]];
|
|
RDDATA1[7:0] <= DATA1_A[VADR[11:4]];
|
end
|
end
|
|
|
always @(posedge MCLK)
|
always @(RDDATA1 or VADR_R)
|
|
case (VADR_R[3:2])
|
|
2'b00 : SET_DAT1 <= RDDATA1[31:0];
|
|
2'b01 : SET_DAT1 <= RDDATA1[63:32];
|
|
2'b10 : SET_DAT1 <= RDDATA1[95:64];
|
|
2'b11 : SET_DAT1 <= RDDATA1[127:96];
|
|
endcase
|
|
|
|
always @(posedge BCLK)
|
if (WRSET1)
|
if (WRSET1)
|
begin
|
begin
|
if (BE_SET[3]) DATA1_D[A_SET] <= DAT_SET[31:24];
|
if (BE_SET[15]) DATA1_P[VADR_R[11:4]] <= DAT_SET[127:120];
|
if (BE_SET[2]) DATA1_C[A_SET] <= DAT_SET[23:16];
|
if (BE_SET[14]) DATA1_O[VADR_R[11:4]] <= DAT_SET[119:112];
|
if (BE_SET[1]) DATA1_B[A_SET] <= DAT_SET[15:8];
|
if (BE_SET[13]) DATA1_N[VADR_R[11:4]] <= DAT_SET[111:104];
|
if (BE_SET[0]) DATA1_A[A_SET] <= DAT_SET[7:0];
|
if (BE_SET[12]) DATA1_M[VADR_R[11:4]] <= DAT_SET[103:96];
|
|
if (BE_SET[11]) DATA1_L[VADR_R[11:4]] <= DAT_SET[95:88];
|
|
if (BE_SET[10]) DATA1_K[VADR_R[11:4]] <= DAT_SET[87:80];
|
|
if (BE_SET[9]) DATA1_J[VADR_R[11:4]] <= DAT_SET[79:72];
|
|
if (BE_SET[8]) DATA1_I[VADR_R[11:4]] <= DAT_SET[71:64];
|
|
if (BE_SET[7]) DATA1_H[VADR_R[11:4]] <= DAT_SET[63:56];
|
|
if (BE_SET[6]) DATA1_G[VADR_R[11:4]] <= DAT_SET[55:48];
|
|
if (BE_SET[5]) DATA1_F[VADR_R[11:4]] <= DAT_SET[47:40];
|
|
if (BE_SET[4]) DATA1_E[VADR_R[11:4]] <= DAT_SET[39:32];
|
|
if (BE_SET[3]) DATA1_D[VADR_R[11:4]] <= DAT_SET[31:24];
|
|
if (BE_SET[2]) DATA1_C[VADR_R[11:4]] <= DAT_SET[23:16];
|
|
if (BE_SET[1]) DATA1_B[VADR_R[11:4]] <= DAT_SET[15:8];
|
|
if (BE_SET[0]) DATA1_A[VADR_R[11:4]] <= DAT_SET[7:0];
|
end
|
end
|
|
|
DCACHE_SM DC_SM(
|
DCACHE_SM DC_SM(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
| Line 343... |
Line 443... |
.ENWR(ENWR),
|
.ENWR(ENWR),
|
.WB_ACC(WB_ACC),
|
.WB_ACC(WB_ACC),
|
.ADR_EQU(ADR_EQU),
|
.ADR_EQU(ADR_EQU),
|
.IC_PREQ(IC_PREQ),
|
.IC_PREQ(IC_PREQ),
|
.CAPDAT(CAPDAT[31:0]),
|
.CAPDAT(CAPDAT[31:0]),
|
.CPU_OUT(DP_Q[59:44]),
|
.CPU_OUT(DP_Q[60:44]),
|
.DMA_CHK(DMA_CHK),
|
.DMA_CHK(DMA_CHK),
|
.IC_VA(IC_VA),
|
.IC_VA(IC_VA),
|
.ICTODC(ICTODC),
|
.ICTODC(ICTODC),
|
.VADR_R(VADR_R[31:12]),
|
.VADR_R(VADR_R[31:12]),
|
.NEW_PTB(NEW_PTB),
|
.NEW_PTB(NEW_PTB),
|
| Line 384... |
Line 484... |
.INVAL_L(CINVAL[0]),
|
.INVAL_L(CINVAL[0]),
|
.CI(CI),
|
.CI(CI),
|
.MMU_HIT(MMU_HIT),
|
.MMU_HIT(MMU_HIT),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.KDET(KDET),
|
.KDET(KDET),
|
.ADDR({RADR[31:28],ADDR}),
|
.ADDR({RADR[31:29],ADDR}),
|
.CFG(CFG),
|
.CFG(CFG),
|
.ENDRAM(ENDRAM),
|
.ENDRAM(ENDRAM),
|
.CVALID(CVALID),
|
.CVALID(CVALID),
|
.TAG0(TAG0),
|
.TAG0(TAG0),
|
.TAG1(TAG1),
|
.TAG1(TAG1),
|
| Line 402... |
Line 502... |
.DC_ILO(RWVAL[2]),
|
.DC_ILO(RWVAL[2]),
|
.UPDATE(UPDATE_C));
|
.UPDATE(UPDATE_C));
|
|
|
DCA_CONTROL DCA_CTRL(
|
DCA_CONTROL DCA_CTRL(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.MCLK(MCLK),
|
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.CA_SET(CA_SET),
|
.CA_SET(CA_SET),
|
.HIT_ALL(HIT_ALL),
|
.HIT_ALL(HIT_ALL),
|
.UPDATE(UPDATE_C),
|
.UPDATE(UPDATE_C),
|
.VADR_R(ADDR[11:7]),
|
.VADR_R(ADDR[11:7]),
|
.DRAM_ACC(DRAM_ACC),
|
.DRAM_ACC(DRAM_ACC),
|
.CUPDATE(CUPDATE),
|
.CUPDATE(CUPDATE),
|
.KILL(KILL),
|
.KILL(KILL),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.WRCFG(WRCFG),
|
.USE_CA(DRAM_A[1]),
|
.WCTRL(WCTRL[1:0]),
|
.INHIBIT(INHIBIT),
|
.INVAL_A(CINVAL[1]),
|
.INVAL_A(CINVAL[1]),
|
|
.MDONE(MDONE),
|
.DAT_CV(DAT_CV),
|
.DAT_CV(DAT_CV),
|
.WADR_CV(WADR_CV),
|
.WADR_CV(WADR_CV),
|
.WE_CV(WE_CV),
|
.WE_CV(WE_CV),
|
.INIT_CA_RUN(INIT_CA_RUN),
|
.INIT_CA_RUN(INIT_CA_RUN),
|
.WRCRAM0(WRCRAM0),
|
.WRCRAM0(WRCRAM0),
|
| Line 473... |
Line 573... |
always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
|
always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
|
|
|
RD_ALIGNER RD_ALI(
|
RD_ALIGNER RD_ALI(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.ACC_OK(ACC_STAT[0]),
|
.ACC_OK(ACC_STAT[0]),
|
.REG_OUT(REG_OUT),
|
.REG_OUT(CTRL_QW[0]),
|
.PACKET(PACKET),
|
.PACKET(PACKET),
|
.RDDATA(LAST_DAT),
|
.RDDATA(LAST_DAT),
|
.SIZE(SIZE),
|
.SIZE(SIZE),
|
.CA_HIT(CA_HIT),
|
.CA_HIT(CA_HIT),
|
.DP_DI(DP_DI),
|
.DP_DI(DP_DI),
|
| Line 500... |
Line 600... |
.VADR_R(VADR_R[31:2]),
|
.VADR_R(VADR_R[31:2]),
|
.MMU_Q(MMU_Q[19:0]),
|
.MMU_Q(MMU_Q[19:0]),
|
.ENBYTE(ENBYTE),
|
.ENBYTE(ENBYTE),
|
.DBG_HIT(DBG_HIT));
|
.DBG_HIT(DBG_HIT));
|
|
|
|
FILTCMP FILT_CMP(
|
|
.RADR({RADR[28:12],VADR_R[11:4]}),
|
|
.DRAMSZ(DRAMSZ),
|
|
.DRAM_A(DRAM_A[28:4]),
|
|
.TAGDAT(TAGDAT),
|
|
.ADR_EQU(ADR_EQU));
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
