| Line 2... |
Line 2... |
//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DECODER.v
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// Filename: DECODER.v
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// Version: 1.1 bug fix
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// Version: 2.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 21 January 2016
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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| Line 39... |
Line 39... |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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|
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module DECODER ( BCLK, BRESET, INT_N, NMI_N, ANZ_VAL, OPREG, CFG, PSR, ACC_DONE, DC_ABORT, IC_ABORT, ACB_ZERO, DONE,
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module DECODER ( BCLK, BRESET, INT_N, NMI_N, ANZ_VAL, OPREG, CFG, PSR, ACC_DONE, DC_ABORT, IC_ABORT, ACB_ZERO, DONE,
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PC_SAVE, STRING, INIT_DONE, ILL, UNDEF, TRAPS, IC_READ, STOP_CINV,
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PC_SAVE, STRING, INIT_DONE, ILL, UNDEF, TRAPS, IC_READ, STOP_CINV,
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GENSTAT, DISP, IMME_Q, DISP_BR, USED, NEW, LOAD_PC, NEXT_PCA, RDAA, RDAB, OPER, START, LD_OUT, LD_DIN, LD_IMME,
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GENSTAT, DISP, IMME_Q, DISP_BR, USED, NEW, LOAD_PC, NEXT_PCA, RDAA, RDAB, OPER, START, LD_OUT, LD_DIN, LD_IMME,
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INFO_AU, ACC_FELD, WREN, WRADR, WMASKE, WR_REG, DETOIP, MMU_UPDATE, RESTART, STOP_IC, RWVAL, ENA_HK, ILO, COP_OP );
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INFO_AU, ACC_FELD, WREN, WRADR, WMASKE, WR_REG, DETOIP, MMU_UPDATE, RESTART, STOP_IC, RWVAL, ENA_HK, ILO, COP_OP,
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PHOUT );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input INT_N,NMI_N; // external inputs
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input INT_N,NMI_N; // external inputs
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input [2:0] ANZ_VAL;
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input [2:0] ANZ_VAL;
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input [55:0] OPREG; // the OPREG contains the bytes to decode, OPREG[55:32] are don't care
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input [55:0] OPREG; // the OPREG contains the bytes to decode, OPREG[55:32] are don't care
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| Line 83... |
Line 84... |
output STOP_IC;
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output STOP_IC;
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output [2:0] RWVAL;
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output [2:0] RWVAL;
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output ENA_HK;
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output ENA_HK;
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output reg ILO;
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output reg ILO;
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output [23:0] COP_OP;
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output [23:0] COP_OP;
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output [7:0] PHOUT; // for Debug purposes, phase_reg output
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reg [31:0] DISP,disp_val;
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reg [31:0] DISP,disp_val;
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reg [10:0] oper_i;
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reg [10:0] oper_i;
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reg [2:0] USED;
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reg [2:0] USED;
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reg [14:0] ACC_FELD;
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reg [14:0] ACC_FELD;
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reg [1:0] ldoreg;
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reg [1:0] ldoreg;
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reg wren_i;
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reg wren_i;
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reg [5:0] wradr_i;
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reg [5:0] wradr_i;
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reg [1:0] wmaske_i;
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reg [1:0] wmaske_i;
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reg [1:0] START;
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reg [1:0] start_i;
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reg [23:0] COP_OP;
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reg [23:0] COP_OP;
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reg spupd_i;
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reg spupd_i;
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reg [3:0] disp_sel;
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reg [3:0] disp_sel;
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reg [52:0] op1_feld;
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reg [52:0] op1_feld;
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reg [47:0] op2_feld;
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reg [47:0] op2_feld;
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| Line 172... |
Line 174... |
wire [7:0] new_ph,ppfp;
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wire [7:0] new_ph,ppfp;
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wire [7:0] new_nx;
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wire [7:0] new_nx;
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wire op_1byte,op_12byte,op_2byte,op_3byte;
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wire op_1byte,op_12byte,op_2byte,op_3byte;
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wire jump;
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wire jump;
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wire short_op,short_def;
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wire short_op,short_def;
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wire opt_imme;
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wire [7:0] opti_byte;
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wire acb_op,acb_flag;
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wire acb_op,acb_flag;
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wire zero,carry_psr,negativ,larger,flag;
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wire zero,carry_psr,negativ,larger,flag;
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wire valid_size;
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wire valid_size;
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wire op_ok;
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wire op_ok;
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wire stop;
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wire stop;
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| Line 253... |
Line 257... |
reg [5:0] hzr_c; // CASE Statement
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reg [5:0] hzr_c; // CASE Statement
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wire [1:0] hzl_a;
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wire [1:0] hzl_a;
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wire [2:0] hzl_b;
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wire [2:0] hzl_b;
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wire [5:0] hzr_a,hzr_b,hzr_s;
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wire [5:0] hzr_a,hzr_b,hzr_s;
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wire hdx_a;
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wire hdx_a;
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wire hdo_b;
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wire [3:0] hdo_a,hdo_c,hdo_e;
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wire [3:0] hdo_a,hdo_c,hdo_e;
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wire [7:0] hdo_d;
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wire [7:0] hdo_d;
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wire [1:0] hdl_b,hdl_d,hdl_f,hdl_g,hdl_h;
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wire [1:0] hdl_b,hdl_d,hdl_f,hdl_g,hdl_h;
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wire [2:0] hdl_a,hdl_c,hdl_e;
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wire [2:0] hdl_a,hdl_c,hdl_e;
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wire [5:0] hdr_a,hdr_b,hdr_c,hdr_d,hdr_e,hdr_f,hdr_g,hdr_m;
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wire [5:0] hdr_a,hdr_b,hdr_c,hdr_d,hdr_e,hdr_f,hdr_g,hdr_m;
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| Line 344... |
Line 347... |
always @(posedge BCLK or negedge BRESET) // the central phase register
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always @(posedge BCLK or negedge BRESET) // the central phase register
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if (!BRESET) phase_reg <= 8'h0;
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if (!BRESET) phase_reg <= 8'h0;
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else
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else
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if (next) phase_reg <= new_op[47:40];
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if (next) phase_reg <= new_op[47:40];
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assign PHOUT = phase_reg; // only to debug
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always @(*) // next switch of micro program counter
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always @(*) // next switch of micro program counter
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casex ({PHASE_0,op_ok,dim_feld[3],di_stat[0]})
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casex ({PHASE_0,op_ok,dim_feld[3],di_stat[0]})
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4'b11_xx : USED = {1'b0,~op_1byte,(op_1byte | op_3byte)};
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4'b11_xx : USED = {1'b0,~op_1byte,(op_1byte | op_3byte)} + {2'd0,opt_imme};
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4'b0x_11 : USED = di_stat[3:1];
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4'b0x_11 : USED = di_stat[3:1];
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default : USED = 3'd0;
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default : USED = 3'd0;
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endcase
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endcase
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// Special phases
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// Special phases
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| Line 529... |
Line 534... |
8'hD2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h89,4'h0,4'h0}; // FLAG
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8'hD2 : op1_feld = {addr_nop, src_x, src_x, 2'b01,2'b00,8'h89,4'h0,4'h0}; // FLAG
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default : op1_feld = {19'hxxxxx,14'hxxxx, 2'b00,2'b00,16'hxxxx};
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default : op1_feld = {19'hxxxxx,14'hxxxx, 2'b00,2'b00,16'hxxxx};
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endcase
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endcase
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assign op_1byte = op1_feld[18] & valid[0];
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assign op_1byte = op1_feld[18] & valid[0];
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assign op_12byte = op1_feld[19] & (valid[1:0] == 2'b11);
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assign op_12byte = op1_feld[19] & valid[1];
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assign new_addr = op1_feld[52:34];
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assign new_addr = op1_feld[52:34];
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assign new_regs = op1_feld[33:20];
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assign new_regs = op1_feld[33:20];
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assign new_ph = op1_feld[15:8];
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assign new_ph = op1_feld[15:8];
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assign new_nx = op1_feld[7:0]; // at Bcond DISP read
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assign new_nx = op1_feld[7:0]; // at Bcond DISP read
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| Line 648... |
Line 653... |
assign disp_ok = ld_disp ? di_stat[0] : 1'b1;
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assign disp_ok = ld_disp ? di_stat[0] : 1'b1;
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always @(dim_feld or OPREG or valid or ANZ_VAL) // Bit 0 is "Data ok", the upper 3 bits are for USED
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always @(dim_feld or OPREG or valid or ANZ_VAL) // Bit 0 is "Data ok", the upper 3 bits are for USED
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casex ({dim_feld[2:1],OPREG[7:6]})
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casex ({dim_feld[2:1],OPREG[7:6]})
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4'b00_xx : di_stat = {3'b001,valid[0]};
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4'b00_xx : di_stat = {3'b001,valid[0]};
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4'b01_xx : di_stat = {3'b010,(valid[1] & valid[0])};
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4'b01_xx : di_stat = {3'b010,valid[1]};
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4'b10_xx : di_stat = {3'b100,ANZ_VAL[2]};
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4'b10_xx : di_stat = {3'b100,ANZ_VAL[2]};
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4'b11_0x : di_stat = {3'b001,valid[0]};
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4'b11_0x : di_stat = {3'b001,valid[0]};
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4'b11_10 : di_stat = {3'b010,(valid[1] & valid[0])};
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4'b11_10 : di_stat = {3'b010,valid[1]};
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4'b11_11 : di_stat = {3'b100,ANZ_VAL[2]};
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4'b11_11 : di_stat = {3'b100,ANZ_VAL[2]};
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endcase
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endcase
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always @(OPREG)
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always @(OPREG)
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casex (OPREG[7:6])
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casex (OPREG[7:6])
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| Line 679... |
Line 684... |
5'b0_1011 : DISP = 32'hFFFF_FFF8; // PUSH QWord
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5'b0_1011 : DISP = 32'hFFFF_FFF8; // PUSH QWord
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5'b0_01xx : DISP = {26'h0,exc_vector,2'b00}; // the exception vector as Offset for INTBASE
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5'b0_01xx : DISP = {26'h0,exc_vector,2'b00}; // the exception vector as Offset for INTBASE
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5'b0_00xx : DISP = {28'h0,disp_sel[1:0],2'b00}; // 0,+4,+8,+12 used with MOD, default is 0
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5'b0_00xx : DISP = {28'h0,disp_sel[1:0],2'b00}; // 0,+4,+8,+12 used with MOD, default is 0
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endcase
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endcase
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always @(short_op or dim_feld or OPREG or op_setcfg or setcfg_lsb)
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always @(*)
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casex ({short_op,dim_feld[2:1]})
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casex ({short_op,dim_feld[2:1]})
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3'b000 : imme_i = op_setcfg ? {28'h0000_00F,OPREG[2:0],setcfg_lsb} : {24'hxx_xxxx,OPREG[7:0]};
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3'b000 : imme_i = op_setcfg ? {28'h0000_00F,OPREG[2:0],setcfg_lsb} : {24'hxx_xxxx,OPREG[7:0]};
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3'b001 : imme_i = {16'hxxxx,OPREG[7:0],OPREG[15:8]};
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3'b001 : imme_i = {16'hxxxx,OPREG[7:0],OPREG[15:8]};
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3'b01x : imme_i = {OPREG[7:0],OPREG[15:8],OPREG[23:16],OPREG[31:24]};
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3'b01x : imme_i = {OPREG[7:0],OPREG[15:8],OPREG[23:16],OPREG[31:24]};
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3'b1xx : imme_i = {{29{OPREG[10]}},OPREG[9:7]}; // for MOVQ etc. only OPREG can be used
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3'b1xx : imme_i = opt_imme ? {24'hxxxx_xx,opti_byte} : {{29{OPREG[10]}},OPREG[9:7]}; // for MOVQ etc. only OPREG can be used
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endcase
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endcase
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assign IMME_Q = store_pc ? PC_SAVE : imme_i;
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assign IMME_Q = store_pc ? PC_SAVE : imme_i;
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// ++++++++++++++ Stack Control +++++++++++++++++
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// ++++++++++++++ Stack Control +++++++++++++++++
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| Line 728... |
Line 733... |
// [12:11] op_type 2 Bit for sort of opcode
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// [12:11] op_type 2 Bit for sort of opcode
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// [10] FL : F=1/L=0
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// [10] FL : F=1/L=0
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// [9:8] original BWD : B=00/W=01/D=11
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// [9:8] original BWD : B=00/W=01/D=11
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// [7:0] opcode: operation code
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// [7:0] opcode: operation code
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assign valid_size = (OPREG[1:0] != 2'b10) & (valid[1:0] == 2'b11); // valid size + valid OPREG-Bytes
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assign valid_size = (OPREG[1:0] != 2'b10) & valid[1]; // valid size + valid OPREG-Bytes
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|
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assign hzl_a = (OPREG[1:0] == 2'b11) ? 2'b10 : OPREG[1:0]; // length field recoded
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assign hzl_a = (OPREG[1:0] == 2'b11) ? 2'b10 : OPREG[1:0]; // length field recoded
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assign hzl_b = {1'b0,OPREG[1:0]}; // standard Length field
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assign hzl_b = {1'b0,OPREG[1:0]}; // standard Length field
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assign hzr_a = {3'b000,OPREG[13:11]}; // SRC2 or SRC1 regfield
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assign hzr_a = {3'b000,OPREG[13:11]}; // SRC2 or SRC1 regfield
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assign hzr_b = {3'b000,OPREG[8:6]}; // SRC2 regfield
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assign hzr_b = {3'b000,OPREG[8:6]}; // SRC2 regfield
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| Line 745... |
Line 750... |
4'b1100 : hzr_c = OPREG[6] ? temp_h : 6'h1C; // CFG special case : LPR : SPR
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4'b1100 : hzr_c = OPREG[6] ? temp_h : 6'h1C; // CFG special case : LPR : SPR
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default : hzr_c = {2'b01,OPREG[10:7]};
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default : hzr_c = {2'b01,OPREG[10:7]};
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endcase
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endcase
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|
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// Unfortunately SETCFG must be implemented : it is transformed to a two byte opcode with one byte IMM operand
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// Unfortunately SETCFG must be implemented : it is transformed to a two byte opcode with one byte IMM operand
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assign setcfg = (OPREG[13:0] == 14'h0B0E) & (valid[1:0] == 2'b11);
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assign setcfg = (OPREG[13:0] == 14'h0B0E) & valid[1];
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|
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always @(*)
|
always @(*)
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casex ({setcfg,OPREG[10:2]})
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casex ({setcfg,OPREG[10:2]})
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// Short-Op Codes , ACB is an ADD with following jump
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// Short-Op Codes , ACB is an ADD with following jump
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10'b0xxxx_x0011 : op2_feld = {6'o11,3'o3,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h40}; // ADDQ ACB
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10'b0xxxx_x0011 : op2_feld = {6'o11,3'o3,6'hxx,hzr_a,hzl_a,hzl_a,5'h14,OPREG[15:11],2'b00,hzl_b,8'h40}; // ADDQ ACB
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| Line 781... |
Line 786... |
endcase
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endcase
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|
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assign op_2byte = (valid_size | setcfg) & ~op2_feld[7]; // it must be for sure shown "Invalid Opcode"
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assign op_2byte = (valid_size | setcfg) & ~op2_feld[7]; // it must be for sure shown "Invalid Opcode"
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|
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// Special case : the quick opcodes with the exception SPR and LPR
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// Special case : the quick opcodes with the exception SPR and LPR
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assign short_op = ((~OPREG[5]) | (OPREG[6:4] == 3'b011)) & (OPREG[3:2] == 2'b11) & valid_size & PHASE_0;
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assign short_op = ((((~OPREG[5]) | (OPREG[6:4] == 3'b011)) & (OPREG[3:2] == 2'b11) & valid_size) | opt_imme) & PHASE_0;
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always @(posedge BCLK) if (PHASE_0) short_op_reg <= short_op;
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always @(posedge BCLK) if (PHASE_0) short_op_reg <= short_op;
|
assign short_def = PHASE_0 ? short_op : short_op_reg; // for the big state machine
|
assign short_def = PHASE_0 ? short_op : short_op_reg; // for the big state machine
|
assign op_sho = (OPREG[6:4] == 3'b011) ? 11'h07A : op_mov; // Special case Scond at Index as Dest. , used only in Phase 0
|
assign op_sho = (OPREG[6:4] == 3'b011) ? 11'h07A : op_mov; // Special case Scond at Index as Dest. , used only in Phase 0
|
|
|
// 2. special case ACB
|
// 2. special case ACB
|
| Line 826... |
Line 831... |
always @(posedge BCLK) if (PHASE_0) setcfg_lsb <= OPREG[15];
|
always @(posedge BCLK) if (PHASE_0) setcfg_lsb <= OPREG[15];
|
|
|
always @(posedge BCLK) if (PHASE_0) jsr_flag <= (OPREG[10:2] == 9'b1100_11111); // JSR : for PUSH
|
always @(posedge BCLK) if (PHASE_0) jsr_flag <= (OPREG[10:2] == 9'b1100_11111); // JSR : for PUSH
|
always @(posedge BCLK) // Bit opcodes to Register and EXT:SRC1 / INS:SRC2
|
always @(posedge BCLK) // Bit opcodes to Register and EXT:SRC1 / INS:SRC2
|
if (PHASE_0) bit_reg <= ((OPREG[3] ? ((OPREG[7:6] == 2'd0) ? OPREG[23:22] : OPREG[18:17]) : OPREG[10:9]) == 2'b00);
|
if (PHASE_0) bit_reg <= ((OPREG[3] ? ((OPREG[7:6] == 2'd0) ? OPREG[23:22] : OPREG[18:17]) : OPREG[10:9]) == 2'b00);
|
always @(posedge BCLK) if (PHASE_0) exin_cmd <= (~OPREG[10] & (OPREG[6:0] == 7'h2E)) & (valid[2:0] == 3'b111);
|
always @(posedge BCLK) if (PHASE_0) exin_cmd <= (~OPREG[10] & (OPREG[6:0] == 7'h2E)) & valid[2];
|
always @(posedge BCLK) if (PHASE_0) extract <= ~OPREG[7];
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always @(posedge BCLK) if (PHASE_0) extract <= ~OPREG[7];
|
always @(posedge BCLK) if (PHASE_0) inss_op <= (OPREG[13:10] == 4'h2) & (OPREG[7:0] == 8'hCE) & (valid[2:0] == 3'b111); // INSS
|
always @(posedge BCLK) if (PHASE_0) inss_op <= (OPREG[13:10] == 4'h2) & (OPREG[7:0] == 8'hCE) & valid[2]; // INSS
|
|
|
// ++++++++++++++ 3 byte opcodes +++++++++++++++++
|
// ++++++++++++++ 3 byte opcodes +++++++++++++++++
|
|
|
// [47:45] Source : [2] TOS=>(SP), [1] Ri => (Ri), [0] 1=access of memory
|
// [47:45] Source : [2] TOS=>(SP), [1] Ri => (Ri), [0] 1=access of memory
|
// [44:42] Destination : like [47:45]
|
// [44:42] Destination : like [47:45]
|
| Line 850... |
Line 855... |
// [9:8] original BWD : B=00/W=01/D=11
|
// [9:8] original BWD : B=00/W=01/D=11
|
// [7:0] opcode: operation code
|
// [7:0] opcode: operation code
|
|
|
assign hdx_a = OPREG[7] ? OPREG[8] : OPREG[10];
|
assign hdx_a = OPREG[7] ? OPREG[8] : OPREG[10];
|
assign hdo_a = OPREG[13:10];
|
assign hdo_a = OPREG[13:10];
|
assign hdo_b = ~hdx_a; // long operation if L
|
|
assign hdo_c = {1'b0,OPREG[10],OPREG[7:6]}; // Format 8 opcodes
|
assign hdo_c = {1'b0,OPREG[10],OPREG[7:6]}; // Format 8 opcodes
|
assign hdo_d = {6'b0101_00,OPREG[10],1'b0}; // CMPM/S or MOVM/S : 8'h52 or 8'h50
|
assign hdo_d = {6'b0101_00,OPREG[10],1'b0}; // CMPM/S or MOVM/S : 8'h52 or 8'h50
|
assign hdo_e = {3'b011,OPREG[10]}; // Special codes for LOGB and SCALB due to DP_OUT datapath
|
assign hdo_e = {3'b011,OPREG[10]}; // Special codes for LOGB and SCALB due to DP_OUT datapath
|
// Definitions of length
|
// Definitions of length
|
assign hdl_a = {1'b0,OPREG[9:8]}; // i size, is used in OPER
|
assign hdl_a = {1'b0,OPREG[9:8]}; // i size, is used in OPER
|
| Line 870... |
Line 874... |
assign hdr_b = {3'b000,OPREG[16:14]}; // SRC2 Integer Register
|
assign hdr_b = {3'b000,OPREG[16:14]}; // SRC2 Integer Register
|
assign hdr_c = hdx_a ? {2'b10,OPREG[21:20],1'b0,OPREG[19]} : {2'b10,OPREG[21:19],1'b1};
|
assign hdr_c = hdx_a ? {2'b10,OPREG[21:20],1'b0,OPREG[19]} : {2'b10,OPREG[21:19],1'b1};
|
assign hdr_d = hdx_a ? {2'b10,OPREG[16:15],1'b0,OPREG[14]} : {2'b10,OPREG[16:14],1'b1};
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assign hdr_d = hdx_a ? {2'b10,OPREG[16:15],1'b0,OPREG[14]} : {2'b10,OPREG[16:14],1'b1};
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assign hdr_e = OPREG[11] ? {2'b10,OPREG[21:20],1'b0,OPREG[19]} : {2'b10,OPREG[21:19],1'b1};
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assign hdr_e = OPREG[11] ? {2'b10,OPREG[21:20],1'b0,OPREG[19]} : {2'b10,OPREG[21:19],1'b1};
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assign hdr_f = OPREG[11] ? {2'b10,OPREG[16:14],1'b1} : {2'b10,OPREG[16:15],1'b0,OPREG[14]};
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assign hdr_f = OPREG[11] ? {2'b10,OPREG[16:14],1'b1} : {2'b10,OPREG[16:15],1'b0,OPREG[14]};
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assign hdr_g = {3'b000,OPREG[16:15],~OPREG[14]}; // exclusiv for DEI/MEI
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assign hdr_g = {3'b000,OPREG[16:15],~OPREG[14]}; // exclusiv for DEI and MEI
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assign hdr_m = {3'b001,OPREG[17:15]}; // MMU Register Index 8-15
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assign hdr_m = {3'b001,OPREG[17:15]}; // MMU Register Index 8-15
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|
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always @(*)
|
always @(*)
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casex (OPREG[13:3])
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casex (OPREG[13:3])
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11'b1000_xx_1100x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MULi
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11'b1000_xx_1100x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MULi
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| Line 883... |
Line 887... |
11'b1x0x_xx_0100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a}; // NEGi,NOTi,ABSi,COMi
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11'b1x0x_xx_0100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a}; // NEGi,NOTi,ABSi,COMi
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11'b010x_xx_1100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,2'b01,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MOVX/ZiW
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11'b010x_xx_1100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,2'b01,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MOVX/ZiW
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11'b011x_xx_1100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MOVX/ZiD
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11'b011x_xx_1100x : op3_feld = {6'o11,3'o1,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h7,hdo_a}; // MOVX/ZiD
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11'b0001_xx_0110x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b00,hdl_a,4'h8,hdo_c}; // FFSi
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11'b0001_xx_0110x : op3_feld = {6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b00,hdl_a,4'h8,hdo_c}; // FFSi
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// Floating Point opcodes
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// Floating Point opcodes
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11'b000x_xx_0011x : op3_feld = {6'o11,hdo_b,2'b01,hdr_a,hdr_d, hdl_b,hdl_d,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVif
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11'b000x_xx_0011x : op3_feld = {6'o11,3'o5,hdr_a,hdr_d, hdl_b,hdl_d,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVif
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11'b010x_xx_0011x : op3_feld = {6'o11, 3'o5,hdr_e,hdr_f, 2'b11,2'b10,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVLF
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11'b010x_xx_0011x : op3_feld = {6'o11, 3'o5,hdr_e,hdr_f, 2'b11,2'b10,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVLF
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11'b011x_xx_0011x : op3_feld = {6'o11, 3'o5,hdr_e,hdr_f, 2'b10,2'b11,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVFL
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11'b011x_xx_0011x : op3_feld = {6'o11, 3'o5,hdr_e,hdr_f, 2'b10,2'b11,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // MOVFL
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11'b10xx_xx_0011x : op3_feld = {6'o11,hdo_b,2'b01,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // ROUNDi,TRUNCi
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11'b10xx_xx_0011x : op3_feld = {6'o11,3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // ROUNDi,TRUNCi
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11'b111x_xx_00111 : op3_feld = {6'o11,hdo_b,2'b01,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // FLOORi
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11'b111x_xx_00111 : op3_feld = {6'o11,3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,4'h9,hdo_a}; // FLOORi
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11'b111x_xx_00110 : op3_feld = {6'o11, 3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,op_cop}; // SEARCH
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11'b111x_xx_00110 : op3_feld = {6'o11, 3'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2'b00,hdl_c,op_cop}; // SEARCH
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11'b0x00_0x_10111 : op3_feld = {6'o11,hdo_b,2'b11,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // ADDf,SUBf
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11'b0x00_0x_10111 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // ADDf,SUBf
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11'bxx00_0x_10110 : op3_feld = {6'o11, 3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,op_cop}; // Coprocessor
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11'bxx00_0x_10110 : op3_feld = {6'o11, 3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,op_cop}; // Coprocessor
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11'b1000_0x_10111 : op3_feld = {6'o11, 3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // DIVf
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11'b1000_0x_10111 : op3_feld = {6'o11, 3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // DIVf
|
11'b1100_0x_10111 : op3_feld = {6'o11,hdo_b,2'b11,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // MULf
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11'b1100_0x_10111 : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // MULf
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11'b0010_0x_1011x : op3_feld = {6'o11,hdo_b,2'b10,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // CMPf
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11'b0010_0x_1011x : op3_feld = {6'o11,3'o6,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // CMPf
|
11'b0001_0x_10111 : op3_feld = {6'o11, 3'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // MOVf
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11'b0001_0x_10111 : op3_feld = {6'o11, 3'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // MOVf
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11'bx101_0x_10111 : op3_feld = {6'o11, 3'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // NEGf,ABSf
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11'bx101_0x_10111 : op3_feld = {6'o11, 3'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_a}; // NEGf,ABSf
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11'b001x_11_00111 : op3_feld = {6'o11,3'o1,hdr_a,fsr_r, 2'b10,2'b10,OPREG[23:19],5'b0,2'b00,3'o3,8'h92}; // LFSR
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11'b001x_11_00111 : op3_feld = {6'o11,3'o1,hdr_a,fsr_r, 2'b10,2'b10,OPREG[23:19],5'b0,2'b00,3'o3,8'h92}; // LFSR
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11'b110x_11_00111 : op3_feld = {6'o11,3'o1,fsr_r,hdr_b, 2'b10,2'b10,5'b0,OPREG[18:14],2'b00,3'o3,8'h9C}; // SFSR
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11'b110x_11_00111 : op3_feld = {6'o11,3'o1,fsr_r,hdr_b, 2'b10,2'b10,5'b0,OPREG[18:14],2'b00,3'o3,8'h9C}; // SFSR
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// MMU opcodes
|
// MMU opcodes
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| Line 914... |
Line 918... |
// Gruppe 2 opcodes
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// Gruppe 2 opcodes
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11'b0x11_xx_1010x : op3_feld = {6'o77,3'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,8'h45}; // MOVUS,MOVSU
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11'b0x11_xx_1010x : op3_feld = {6'o77,3'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,8'h45}; // MOVUS,MOVSU
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11'b000x_xx_1100x : op3_feld = {6'o66,3'o0,hdr_a,hdr_b, 2'bxx,2'b10,OPREG[23:14],2'b10,hdl_c, hdo_d}; // MOVM/CMPM
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11'b000x_xx_1100x : op3_feld = {6'o66,3'o0,hdr_a,hdr_b, 2'bxx,2'b10,OPREG[23:14],2'b10,hdl_c, hdo_d}; // MOVM/CMPM
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11'b001x_0x_1111x : op3_feld = {6'o11,3'o2,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b10,hdl_e,4'hC,hdo_a}; // DOTf,POLYf
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11'b001x_0x_1111x : op3_feld = {6'o11,3'o2,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b10,hdl_e,4'hC,hdo_a}; // DOTf,POLYf
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11'b0101_0x_1111x : op3_feld = {6'o11,3'o5,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_e}; // LOGB
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11'b0101_0x_1111x : op3_feld = {6'o11,3'o5,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_e}; // LOGB
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11'b0100_0x_1111x : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b10,hdl_e,4'hB,hdo_e}; // SCALB
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11'b0100_0x_1111x : op3_feld = {6'o11,3'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2'b00,hdl_e,4'hB,hdo_e}; // SCALB
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11'b0011_xx_1100x : op3_feld = {6'o50,3'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h7,hdo_a}; // EXTS
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11'b0011_xx_1100x : op3_feld = {6'o50,3'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h7,hdo_a}; // EXTS
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11'bxxx0_xx_1110x : op3_feld = {6'o71,3'o2,hdr_a,hdr_b, hdl_h,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h8,hdo_c}; // CHECK
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11'bxxx0_xx_1110x : op3_feld = {6'o71,3'o2,hdr_a,hdr_b, hdl_h,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h8,hdo_c}; // CHECK
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11'b0x1x_xx_0100x : op3_feld = (OPREG[18:17] == 2'b00) ? // target is register => standard flow
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11'b0x1x_xx_0100x : op3_feld = (OPREG[18:17] == 2'b00) ? // target is register => standard flow
|
{6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a} // SBIT/CBIT
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{6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a} // SBIT/CBIT
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: {6'o14,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b10,hdl_a,4'h6,hdo_a};
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: {6'o14,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b10,hdl_a,4'h6,hdo_a};
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11'b1110_xx_0100x : op3_feld = (OPREG[18:17] == 2'b00) ? // target is register => standard flow
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11'b1110_xx_0100x : op3_feld = (OPREG[18:17] == 2'b00) ? // target is register => standard flow
|
{6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a} // IBIT
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{6'o11,3'o3,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a} // IBIT
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: {6'o14,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b10,hdl_a,4'h6,hdo_a};
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: {6'o14,3'o3,hdr_a,hdr_b, hdl_b,2'b00,OPREG[23:14],2'b10,hdl_a,4'h6,hdo_a};
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11'b1x11_xx_0100x : op3_feld = {6'o11,3'o7,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h6,hdo_a}; // ADDP,SUBP
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11'b1x11_xx_0100x : op3_feld = {6'o11,3'o7,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b00,hdl_a,4'h7,3'd0,OPREG[12]}; // ADDP,SUBP
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11'bxxx0_xx_0010x : op3_feld = {6'o40,3'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h8,hdo_c}; // EXT
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11'bxxx0_xx_0010x : op3_feld = {6'o40,3'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2'b10,hdl_c,4'h8,hdo_c}; // EXT
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11'bxxx0_xx_1010x : op3_feld = {6'o14,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_c}; // INS
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11'bxxx0_xx_1010x : op3_feld = {6'o14,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_c}; // INS
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11'b0010_xx_1100x : op3_feld = {6'o14,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_a}; // INSS
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11'b0010_xx_1100x : op3_feld = {6'o14,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_a}; // INSS
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11'bxxx0_xx_0110x : op3_feld = {6'o61,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_c}; // CVTP no Opcode
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11'bxxx0_xx_0110x : op3_feld = {6'o61,3'o0,hdr_a,hdr_b, hdl_b,2'b10,OPREG[23:14],2'b10, 3'o3,4'h8,hdo_c}; // CVTP no Opcode
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11'bxxx1_xx_0010x : op3_feld = {6'o11,3'o2,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b10, 3'o3,8'h84}; // INDEX
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11'bxxx1_xx_0010x : op3_feld = {6'o11,3'o2,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2'b10, 3'o3,8'h84}; // INDEX
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| Line 936... |
Line 940... |
11'b1001_11_0001x : op3_feld = {6'o11,3'o1,hdr_a,temp_h,2'b10,2'b10,OPREG[23:19],5'b0,2'b00,3'o3,8'h45}; // CINV
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11'b1001_11_0001x : op3_feld = {6'o11,3'o1,hdr_a,temp_h,2'b10,2'b10,OPREG[23:19],5'b0,2'b00,3'o3,8'h45}; // CINV
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|
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default : op3_feld = {40'hxx_xxxx_xxxx,4'hA,4'hx};
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default : op3_feld = {40'hxx_xxxx_xxxx,4'hA,4'hx};
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endcase
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endcase
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assign op_3byte = (valid[2:0] == 3'b111) & (OPREG[2:0] == 3'b110) & (op3_feld[7:4] != 4'hA); // valid for all incl. CUSTOM
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assign op_3byte = valid[2] & (OPREG[2:0] == 3'b110) & (op3_feld[7:4] != 4'hA); // valid for all incl. CUSTOM
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|
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// +++++++++++++ Evaluation for 2 and 3 byte opcodes ++++++++++++++++++
|
// +++++++++++++ Evaluation for 2 and 3 byte opcodes ++++++++++++++++++
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|
|
// for one byte opcodes special treatmant neccessary
|
// for one byte opcodes special treatmant neccessary
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assign opc_bits = op_3byte ? op3_feld : op2_feld;
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assign opc_bits = op_3byte ? op3_feld : op2_feld;
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| Line 975... |
Line 979... |
assign opera = op_feld[10:0];
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assign opera = op_feld[10:0];
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assign dest_r = src_2[5:0];
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assign dest_r = src_2[5:0];
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assign dest_rl = {dest_r[5:1],1'b0};
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assign dest_rl = {dest_r[5:1],1'b0};
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|
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// ++++++++++++++++++++++++++++ Immediate Optimization +++++++++++++++++++++++++++++++++++
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// 3 Byte Immediate
|
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assign opt_imme = (valid[2] & (OPREG[1:0] == 2'd0) & (OPREG[15:11] == 5'b10100) &
|
|
// ADD,ADDC,SUB,SUBC,BIC,OR,AND,XOR CMP MOV
|
|
( ((OPREG[10:8] != 3'b111) & (~OPREG[2] | (OPREG[5:2] == 4'h1) | (OPREG[5:2] == 4'h5))) // not ADDR und TBIT
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|
|((OPREG[6:2] == 5'b11111) & (OPREG[8:7] == 2'b10) & (OPREG[10:9] != 2'b11)))) // BICPSR,BISPSR,ADJSP and ~CASE
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// 4 not Scaled Index Immediate
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|
| (ANZ_VAL[2] & (OPREG[18:16] != 3'b111) & (OPREG[23:19] == 5'b10100) &
|
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( ((OPREG[7:0] == 8'h4E) & ~OPREG[13] & ~OPREG[11]) // ROT,ASH,LSH but not NEG,NOT,ABS,COM
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|
|((OPREG[7:0] == 8'hCE) & (OPREG[13:12] == 2'b01) & (OPREG[9:8] == 2'd0)))); // MOVX/ZBi
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|
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assign opti_byte = (OPREG[1:0] == 2'b10) ? OPREG[31:24] : OPREG[23:16];
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|
|
// +++++++++++++++++++++++++ Coprocessor operations field ++++++++++++++++++++++++++++++
|
// +++++++++++++++++++++++++ Coprocessor operations field ++++++++++++++++++++++++++++++
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|
|
always @(posedge BCLK) if (PHASE_0) COP_OP <= OPREG[23:0];
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always @(posedge BCLK) if (PHASE_0) COP_OP <= OPREG[23:0];
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|
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// +++++++++++++++++++++++++ Special signals for LMR and CINV ++++++++++++++++++++++++++
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// +++++++++++++++++++++++++ Special signals for LMR and CINV ++++++++++++++++++++++++++
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| Line 1374... |
Line 1392... |
{8'h1F,10'bxx_xxxx_xxx0}: // CMP done -> phase 0
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{8'h1F,10'bxx_xxxx_xxx0}: // CMP done -> phase 0
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new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b10, 4'h0}; // no ACB
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new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b10, 4'h0}; // no ACB
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{8'h1F,10'bxx_xxxx_x0x1}: // operation closed , data into register
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{8'h1F,10'bxx_xxxx_x0x1}: // operation closed , data into register
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new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b00, 4'h0}; // no ACB
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new_op = {addr_nop,8'h00, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b00, 4'h0}; // no ACB
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{8'h1F,10'bxx_xxxx_x101}: // operation closed , data into memory - first calculate address phase 32+x
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{8'h1F,10'bxx_xxxx_x101}: // operation closed , data into memory - first calculate address phase 32+x
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new_op = {adwr2, phwr2, irrw2,rega2, 1'b0,dest_r, opera, 2'b00,2'b00, nxrw2};
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new_op = {adwr2, phwr2, irrw2,rega2, 1'b0,dest_r, opera, 2'b00,2'b10, nxrw2};
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{8'h1F,10'bxx_xxxx_x111}: // operation closed , data into memory - address reuse phase 39 ACC_DONE
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{8'h1F,10'bxx_xxxx_x111}: // operation closed , data into memory - address reuse phase 39 ACC_DONE
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new_op = {re_wr, 8'h27, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b00, 4'b0001};
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new_op = {re_wr, 8'h27, src_x,src_x, 1'b0,dest_r, opera, 2'b00,2'b10, 4'b0001};
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// Destination address calculate
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// Destination address calculate
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// Phase 37 : wait for data and Disp2 for External addressing : part 2 EA = (MOD+4)+4*DISP1
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// Phase 37 : wait for data and Disp2 for External addressing : part 2 EA = (MOD+4)+4*DISP1
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// next phase fix : 38
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// next phase fix : 38
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{8'h25,10'bxx_xxxx_xxxx}: new_op = {exr11, 8'h26, src_x,imme , 1'b0,dest_x, opera, 2'b00,2'b00, 4'b1111};
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{8'h25,10'bxx_xxxx_xxxx}: new_op = {exr11, 8'h26, src_x,imme , 1'b0,dest_x, opera, 2'b00,2'b00, 4'b1111};
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| Line 1693... |
Line 1711... |
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// WMASKE : SP always 32 Bit, opcodes in Format 1, Reg-Nr. >31 , INDEX opcodes and the CHECK operand too
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// WMASKE : SP always 32 Bit, opcodes in Format 1, Reg-Nr. >31 , INDEX opcodes and the CHECK operand too
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assign WMASKE = {(spupd | format1 | wradr_i[5] | wmaske_i[1] | index_cmd | (oper_i[7:0] == 8'h83)),wmaske_i[0]};
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assign WMASKE = {(spupd | format1 | wradr_i[5] | wmaske_i[1] | index_cmd | (oper_i[7:0] == 8'h83)),wmaske_i[0]};
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assign WRADR = spupd ? {~stack[5],stack[4:0]} : wradr_i;
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assign WRADR = spupd ? {~stack[5],stack[4:0]} : wradr_i;
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assign WREN = (spupd | wren_i) & no_trap;
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assign WREN = (spupd | wren_i) & no_trap;
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assign START = no_trap ? start_i : 2'b0;
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assign OPER = spupd ? op_adr : oper_i;
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assign OPER = spupd ? op_adr : oper_i;
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always @(posedge BCLK) ACC_FELD[14] <= next & (new_op[64] | new_op[63] | new_op[62]); // NEWACC is important
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always @(posedge BCLK) ACC_FELD[14] <= next & (new_op[64] | new_op[63] | new_op[62]); // NEWACC is important
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always @(posedge BCLK) ACC_FELD[9] <= next & new_op[62]; // LDEA is only one pulse
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always @(posedge BCLK) ACC_FELD[9] <= next & new_op[62]; // LDEA is only one pulse
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always @(posedge BCLK) START <= next ? new_op[7:6] : 2'b00;
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always @(posedge BCLK) start_i <= next ? new_op[7:6] : 2'b00;
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always @(posedge BCLK) ldoreg <= next ? new_op[5:4] : 2'b00; // [1] = LD_OUT , [0] = LD_LDQ
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always @(posedge BCLK) ldoreg <= next ? new_op[5:4] : 2'b00; // [1] = LD_OUT , [0] = LD_LDQ
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always @(posedge BCLK) wren_i <= next & new_op[25] & ~new_op[7]; // only if no START[1] from Long-Op
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always @(posedge BCLK) wren_i <= next & new_op[25] & ~new_op[7]; // only if no START[1] from Long-Op
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assign LD_OUT = {(ldoreg[1] & no_trap),ldoreg[0]}; // [1] = LD_OUT (for CMP too) , [0] = LD_LDQ
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assign LD_OUT = {(ldoreg[1] & no_trap),ldoreg[0]}; // [1] = LD_OUT (for CMP too) , [0] = LD_LDQ
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