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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DECODER.v
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// Filename: DECODER.v
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// Version: 3.0
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// Version: 3.2 bug fix
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// History: 2.0 of 11 August 2016
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// History: 3.0 of 2 December 2018
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// 2.0 of 11 August 2016
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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// Date: 17 January 2021
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//
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//
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// Copyright (C) 2018 Udo Moeller
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// Copyright (C) 2021 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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assign jump = (ex_br_op[0] & branch) | (acb_reg & ~ACB_ZERO) | ex_br_op[1];
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assign jump = (ex_br_op[0] & branch) | (acb_reg & ~ACB_ZERO) | ex_br_op[1];
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always @(posedge BCLK) ldpc_phase <= (phase_reg == 8'h3E) // PC load at CXP/Traps , all one clock cycle guaranted
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always @(posedge BCLK) ldpc_phase <= (phase_reg == 8'h3E) // PC load at CXP/Traps , all one clock cycle guaranted
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| (phase_reg == 8'h43) // PC load at RXP
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| (phase_reg == 8'h43) // PC load at RXP
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| ((phase_reg == 8'h49) & reti_flag) // PC load at RETI
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| ((phase_reg == 8'h49) & reti_flag) // PC load at RETI
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| (phase_reg == 8'h4E) // PC load at RETT
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| ((phase_reg == 8'h4E) & next) // PC load at RETT - here not one clock cycle guaranted
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| (phase_reg == 8'h66) // PC load at JUMP/JSR/CASE
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| (phase_reg == 8'h66) // PC load at JUMP/JSR/CASE
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| (phase_reg == 8'h7B); // PC load at DE = Direct Exception
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| (phase_reg == 8'h7B); // PC load at DE = Direct Exception
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assign NEW = ((phase_reg == 8'd1) & jump & di_stat[0]) | LOAD_PC;
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assign NEW = ((phase_reg == 8'd1) & jump & di_stat[0]) | LOAD_PC;
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assign LOAD_PC = ((phase_reg == 8'h2B) & di_stat[0]) // only one pulse, but DISP must be ok => di_stat[0] (RET)
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assign LOAD_PC = ((phase_reg == 8'h2B) & di_stat[0]) // only one pulse, but DISP must be ok => di_stat[0] (RET)
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