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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ICACHE.v
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// Filename: ICACHE.v
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// Project: M32632
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// Version: 3.2 bug fix
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// Version: 3.1 bug fix of 25 February 2019
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// History: 3.1 bug fix of 25 February 2019
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// History: 3.0 Cache Interface reworked
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// 3.0 Cache Interface reworked
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// 2.0 50 MHz release of 14 August 2016
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// 2.0 50 MHz release of 14 August 2016
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Author: Udo Moeller
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// Date: 17 January 2021
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// Date: 8 July 2017
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//
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//
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// Copyright (C) 2019 Udo Moeller
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// Copyright (C) 2021 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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wire [23:0] NEWCVAL;
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wire [23:0] NEWCVAL;
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wire KILL_C,KILL_K;
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wire KILL_C,KILL_K;
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wire RMW;
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wire RMW;
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wire [31:0] CAP_Q;
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wire [31:0] CAP_Q;
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wire [28:12] TAGDAT;
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wire [28:12] TAGDAT;
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wire clr_up;
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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reg [127:0] DATA0 [0:255]; // Data Set 0 : 4 kBytes
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reg [127:0] DATA0 [0:255]; // Data Set 0 : 4 kBytes
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reg [127:0] RDDATA0;
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reg [127:0] RDDATA0;
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assign ICTODC[3] = USER;
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assign ICTODC[3] = USER;
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assign VADR[31:12] = IVAR_MUX ? VADR_D : VADR_I[31:12];
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assign VADR[31:12] = IVAR_MUX ? VADR_D : VADR_I[31:12];
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assign VADR[11:0] = VADR_I[11:0];
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assign VADR[11:0] = VADR_I[11:0];
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always @(posedge BCLK) VADR_R <= VADR;
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always @(posedge BCLK) VADR_R[23:0] <= VADR[23:0];
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assign clr_up = ~(DRAMSZ == 3'd0);
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always @(posedge BCLK or negedge clr_up)
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if (!clr_up) VADR_R[31:24] <= 8'd0;
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else VADR_R[31:24] <= VADR[31:24];
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always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
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always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
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always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
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always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
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