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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ICACHE.v
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// Filename: ICACHE.v
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// Version: 1.0
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// Version: 2.0
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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// Modules contained in this file:
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// Modules contained in this file:
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// ICACHE the instruction cache of M32632
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// ICACHE the instruction cache of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ICACHE( BCLK, MCLK, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
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module ICACHE( BCLK, MCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
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KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR, WADDR,
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KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR, WADDR,
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WCTRL, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
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WCTRL, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
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DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
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DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
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input BCLK;
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input BCLK;
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input MCLK;
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input MCLK;
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input [2:0] DRAMSZ;
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input MDONE;
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input MDONE;
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input BRESET;
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input BRESET;
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input READ_I;
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input READ_I;
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input IO_READY;
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input IO_READY;
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input PSR_USER;
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input PSR_USER;
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reg [15:0] TAG0;
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reg [15:0] TAG0;
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reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [15:0] TAG1;
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reg [15:0] TAG1;
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reg [23:0] CA_VALID [0:31]; // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
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wire [23:0] CVALID;
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reg [23:0] CVALID;
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_Q;
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reg [35:0] MMU_Q;
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [15:0] KTAG0;
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reg [15:0] KTAG0;
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reg [15:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [15:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [15:0] KTAG1;
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reg [15:0] KTAG1;
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reg [23:0] KCA_VALID [0:31]; // Kollision Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
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wire [23:0] KCVALID;
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reg [23:0] KCVALID;
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assign READ = READ_I & ~HOLD_ON & RUN_ICRD;
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assign READ = READ_I & ~HOLD_ON & RUN_ICRD;
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assign WRITE = 1'b0;
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assign WRITE = 1'b0;
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assign RMW = 1'b0;
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assign RMW = 1'b0;
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always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
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always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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always @(posedge BCLK) CVALID <= CA_VALID[V_ADR[11:7]];
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NEU_VALID VALID_RAM(
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.BCLK(BCLK),
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always @(negedge BCLK) if (WE_CV) CA_VALID[ACV] <= D_CV;
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.VALIN(D_CV),
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.WADR(ACV),
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.WREN(WE_CV),
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.RADR(V_ADR[11:7]),
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.VALOUT(CVALID) );
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
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always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
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.INVAL_L(CINVAL[0]),
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.INVAL_L(CINVAL[0]),
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.CI(CI),
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.CI(CI),
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.MMU_HIT(MMU_HIT),
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.MMU_HIT(MMU_HIT),
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.WRITE(WRITE),
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.WRITE(WRITE),
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.KDET(1'b0),
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.KDET(1'b0),
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.ADDR({RADR[27:12],VADR_R[11:4]}),
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.ADDR({RADR[31:12],VADR_R[11:4]}),
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.CFG(CFG),
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.CFG(CFG),
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.ENDRAM(ENDRAM),
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.ENDRAM(ENDRAM),
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.CVALID(CVALID),
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.CVALID(CVALID),
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.TAG0(TAG0),
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.TAG0(TAG0),
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.TAG1(TAG1),
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.TAG1(TAG1),
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.CA_HIT(CA_HIT),
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.CA_HIT(CA_HIT),
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.CA_SET(CA_SET),
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.CA_SET(CA_SET),
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.WB_ACC(),
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.WB_ACC(),
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.USE_CA(USE_CA),
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.USE_CA(USE_CA),
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.IOSEL(RADR[31:28]),
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.DRAMSZ(DRAMSZ),
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.IO_SPACE(IO_SPACE),
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.IO_SPACE(IO_SPACE),
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.DC_ILO(1'b0),
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.DC_ILO(1'b0),
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.KILL(KILL_C),
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.KILL(KILL_C),
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.UPDATE(UPDATE_C));
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.UPDATE(UPDATE_C));
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.IC_PREQ(IC_PREQ),
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.IC_PREQ(IC_PREQ),
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.HIT_ALL(HIT_ALL));
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.HIT_ALL(HIT_ALL));
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// +++++++++++++++++++++++++ Kollision Valid +++++++++++++++
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// +++++++++++++++++++++++++ Kollision Valid +++++++++++++++
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always @(posedge BCLK) KCVALID <= KCA_VALID[KOLLI_A[11:7]];
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NEU_VALID KOL_VAL(
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.BCLK(BCLK),
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always @(negedge BCLK) if (WE_CV) KCA_VALID[ACV] <= D_CV;
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.VALIN(D_CV),
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.WADR(ACV),
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.WREN(WE_CV),
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.RADR(KOLLI_A[11:7]),
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.VALOUT(KCVALID) );
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// +++++++++++++++++++++++++ Kollision Tag Set 0 +++++++++++
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// +++++++++++++++++++++++++ Kollision Tag Set 0 +++++++++++
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always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
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always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
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