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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ICACHE.v
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// Filename: ICACHE.v
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// Version: 2.0
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// Version: 3.0 Cache Interface reworked
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// History: 1.0 first release of 30 Mai 2015
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// History: 2.0 50 MHz release of 14 August 2016
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// Date: 14 August 2016
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// 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// ICACHE the instruction cache of M32632
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// ICACHE the instruction cache of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ICACHE( BCLK, MCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
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module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
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KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR, WADDR,
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KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR,
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WCTRL, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
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INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
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DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
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DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
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input BCLK;
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input BCLK;
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input MCLK;
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input [2:0] DRAMSZ;
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input [2:0] DRAMSZ;
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input MDONE;
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input MDONE;
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input BRESET;
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input BRESET;
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input READ_I;
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input READ_I;
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input IO_READY;
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input IO_READY;
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| Line 56... |
Line 56... |
input PTB_SEL;
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input PTB_SEL;
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input DRAM_WR;
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input DRAM_WR;
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input KDET;
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input KDET;
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input HOLD;
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input HOLD;
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input [1:0] CFG;
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input [1:0] CFG;
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input [31:0] DRAM_Q;
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input [127:0] DRAM_Q;
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input [1:0] CINVAL;
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input [1:0] CINVAL;
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input [1:0] IC_SIGS;
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input [1:0] IC_SIGS;
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input [31:0] IO_Q;
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input [31:0] IO_Q;
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input [1:0] IVAR;
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input [1:0] IVAR;
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input [27:4] KOLLI_A;
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input [28:4] KOLLI_A;
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input [3:0] MCR_FLAGS;
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input [3:0] MCR_FLAGS;
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input [23:0] MMU_DIN;
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input [23:0] MMU_DIN;
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input [31:0] VADR;
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input [31:0] VADR;
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input [11:2] WADDR;
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input INHIBIT;
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input [2:0] WCTRL;
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input ENA_HK;
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input ENA_HK;
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input ENDRAM;
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input ENDRAM;
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output IO_RD;
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output IO_RD;
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output DRAM_ACC;
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output DRAM_ACC;
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Line 80... |
output KOLLISION;
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output KOLLISION;
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output STOP_CINV;
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output STOP_CINV;
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output [31:0] IC_DQ;
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output [31:0] IC_DQ;
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output [31:12] IC_VA;
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output [31:12] IC_VA;
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output [3:0] ICTODC;
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output [3:0] ICTODC;
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output reg [27:0] DRAM_A;
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output reg [28:0] DRAM_A;
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output reg [31:0] IO_A;
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output reg [31:0] IO_A;
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reg [31:0] VADR_R;
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reg [31:0] VADR_R;
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reg [31:0] CAPDAT;
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reg [31:0] CAPDAT;
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reg [31:0] DFFE_IOR;
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reg [31:0] DFFE_IOR;
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Line 139... |
wire [3:0] RADR_MV;
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wire [3:0] RADR_MV;
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wire [3:0] WADR_MV;
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wire [3:0] WADR_MV;
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wire [23:0] NEWCVAL;
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wire [23:0] NEWCVAL;
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wire KILL_C,KILL_K;
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wire KILL_C,KILL_K;
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wire RMW;
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wire RMW;
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wire [31:0] CAP_Q;
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wire [28:12] TAGDAT;
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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reg [31:0] DATA0 [0:1023]; // Data Set 0 : 4 kBytes
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reg [127:0] DATA0 [0:255]; // Data Set 0 : 4 kBytes
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reg [127:0] RDDATA0;
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reg [31:0] SET_DAT0;
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reg [31:0] SET_DAT0;
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reg [31:0] DATA1 [0:1023]; // Data Set 1 : 4 kBytes
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reg [127:0] DATA1 [0:255]; // Data Set 1 : 4 kBytes
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reg [127:0] RDDATA1;
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reg [31:0] SET_DAT1;
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reg [31:0] SET_DAT1;
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reg [15:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 16 bits
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reg [16:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 17 bits
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reg [15:0] TAG0;
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reg [16:0] TAG0;
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reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [16:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 17 bits
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reg [15:0] TAG1;
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reg [16:0] TAG1;
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wire [23:0] CVALID;
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wire [23:0] CVALID;
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_Q;
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reg [35:0] MMU_Q;
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MVALID;
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reg [31:0] MVALID;
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reg [15:0] KTAGSET_0 [0:255]; // Kollision Tag Set for Data Set 0 : 256 entries of 16 bits
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reg [16:0] KTAGSET_0 [0:255]; // Kollision Tag Set for Data Set 0 : 256 entries of 17 bits
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reg [15:0] KTAG0;
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reg [16:0] KTAG0;
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reg [15:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [16:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 17 bits
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reg [15:0] KTAG1;
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reg [16:0] KTAG1;
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wire [23:0] KCVALID;
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wire [23:0] KCVALID;
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assign READ = READ_I & ~HOLD_ON & RUN_ICRD;
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assign READ = READ_I & ~HOLD_ON & RUN_ICRD;
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assign WRITE = 1'b0;
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assign WRITE = 1'b0;
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| Line 213... |
Line 216... |
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always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
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always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
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always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
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always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
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always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET};
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always @(posedge BCLK) if (LD_DRAM_A) DRAM_A <= {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET};
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always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};
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always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};
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always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
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always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) HOLD_ON <= 1'b0;
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if (!BRESET) HOLD_ON <= 1'b0;
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else HOLD_ON <= (DATA_HOLD & DFF_HDFF1) | (HOLD_ON & DATA_HOLD);
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else HOLD_ON <= (DATA_HOLD & DFF_HDFF1) | (HOLD_ON & DATA_HOLD);
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always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
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DMUX DMUX_4TO1 (
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.DRAM_Q(DRAM_Q),
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.ADDR(VADR_R[3:2]),
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.CAP_Q(CAP_Q) );
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always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
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FILTCMP FILT_CMP(
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.RADR({RADR[28:12],VADR_R[11:4]}),
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.DRAMSZ(DRAMSZ),
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.DRAM_A(25'd0),
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.TAGDAT(TAGDAT),
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.ADR_EQU());
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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NEU_VALID VALID_RAM(
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NEU_VALID VALID_RAM(
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.BCLK(BCLK),
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.BCLK(BCLK),
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| Line 239... |
Line 254... |
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
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always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
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always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
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always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;
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// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
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// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
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always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];
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always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];
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always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
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always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;
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// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
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// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
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always @(posedge BCLK) SET_DAT0 <= DATA0[VADR[11:2]];
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always @(posedge BCLK) RDDATA0 <= DATA0[VADR[11:4]];
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always @(RDDATA0 or VADR_R)
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case (VADR_R[3:2])
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2'b00 : SET_DAT0 <= RDDATA0[31:0];
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2'b01 : SET_DAT0 <= RDDATA0[63:32];
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2'b10 : SET_DAT0 <= RDDATA0[95:64];
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2'b11 : SET_DAT0 <= RDDATA0[127:96];
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endcase
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always @(posedge MCLK) if (WRSET0) DATA0[WADDR] <= DRAM_Q;
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always @(posedge BCLK) if (WRSET0) DATA0[VADR_R[11:4]] <= DRAM_Q;
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// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
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// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
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always @(posedge BCLK) SET_DAT1 <= DATA1[VADR[11:2]];
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always @(posedge BCLK) RDDATA1 <= DATA1[VADR[11:4]];
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always @(posedge MCLK) if (WRSET1) DATA1[WADDR] <= DRAM_Q;
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always @(RDDATA1 or VADR_R)
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case (VADR_R[3:2])
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2'b00 : SET_DAT1 <= RDDATA1[31:0];
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2'b01 : SET_DAT1 <= RDDATA1[63:32];
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2'b10 : SET_DAT1 <= RDDATA1[95:64];
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2'b11 : SET_DAT1 <= RDDATA1[127:96];
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endcase
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always @(posedge BCLK) if (WRSET1) DATA1[VADR_R[11:4]] <= DRAM_Q;
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CA_MATCH DCA_COMPARE(
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CA_MATCH DCA_COMPARE(
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.INVAL_L(CINVAL[0]),
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.INVAL_L(CINVAL[0]),
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.CI(CI),
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.CI(CI),
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.MMU_HIT(MMU_HIT),
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.MMU_HIT(MMU_HIT),
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| Line 283... |
Line 314... |
.KILL(KILL_C),
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.KILL(KILL_C),
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.UPDATE(UPDATE_C));
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.UPDATE(UPDATE_C));
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DCA_CONTROL DCA_CTRL(
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DCA_CONTROL DCA_CTRL(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.MCLK(1'b0),
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.WRCFG(1'b1),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.CA_SET(CA_SET),
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.CA_SET(CA_SET),
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.HIT_ALL(HIT_ALL),
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.HIT_ALL(HIT_ALL),
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.UPDATE(UPCD),
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.UPDATE(UPCD),
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.VADR_R(VADR_R[11:7]),
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.VADR_R(VADR_R[11:7]),
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.DRAM_ACC(DRAM_ACC),
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.DRAM_ACC(DRAM_ACC),
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.CUPDATE(CUPDATE),
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.CUPDATE(CUPDATE),
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.KILL(KILL),
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.KILL(KILL),
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.WRITE(WRITE),
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.WRITE(WRITE),
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.WCTRL(WCTRL[1:0]),
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.USE_CA(DRAM_A[1]),
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.INHIBIT(INHIBIT),
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.INVAL_A(CINVAL[1]),
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.INVAL_A(CINVAL[1]),
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.MDONE(MDONE),
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.DAT_CV(D_CV),
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.DAT_CV(D_CV),
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.WADR_CV(A_CV),
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.WADR_CV(A_CV),
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.WE_CV(WE_CV),
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.WE_CV(WE_CV),
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.INIT_CA_RUN(INIT_CA_RUN),
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.INIT_CA_RUN(INIT_CA_RUN),
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.WRCRAM0(WRCRAM0),
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.WRCRAM0(WRCRAM0),
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| Line 345... |
Line 376... |
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// +++++++++++++++++++++++++ Kollision Tag Set 0 +++++++++++
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// +++++++++++++++++++++++++ Kollision Tag Set 0 +++++++++++
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always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
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always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
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always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= RADR[27:12];
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always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= TAGDAT;
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// +++++++++++++++++++++++++ Kollision Tag Set 1 +++++++++++
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// +++++++++++++++++++++++++ Kollision Tag Set 1 +++++++++++
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always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];
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always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];
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always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= RADR[27:12];
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always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= TAGDAT;
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KOLDETECT KOLLOGIK(
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KOLDETECT KOLLOGIK(
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.DRAM_WR(DRAM_WR),
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.DRAM_WR(DRAM_WR),
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.BCLK(BCLK),
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.BCLK(BCLK),
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.READ_I(READ_I),
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.READ_I(READ_I),
|
