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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ICACHE.v
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// Filename: ICACHE.v
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// Version: 3.0 Cache Interface reworked
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// Project: M32632
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// History: 2.0 50 MHz release of 14 August 2016
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// Version: 3.1 bug fix of 25 February 2019
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// History: 3.0 Cache Interface reworked
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// 2.0 50 MHz release of 14 August 2016
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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// Author: Udo Moeller
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// Date: 8 July 2017
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//
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//
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// Copyright (C) 2018 Udo Moeller
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// Copyright (C) 2019 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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// ICACHE the instruction cache of M32632
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// ICACHE the instruction cache of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
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module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
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KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR,
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KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, IVAR_MUX, VADR_D, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR_I,
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INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
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INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
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DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
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DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
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input BCLK;
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input BCLK;
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input [2:0] DRAMSZ;
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input [2:0] DRAMSZ;
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input [127:0] DRAM_Q;
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input [127:0] DRAM_Q;
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input [1:0] CINVAL;
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input [1:0] CINVAL;
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input [1:0] IC_SIGS;
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input [1:0] IC_SIGS;
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input [31:0] IO_Q;
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input [31:0] IO_Q;
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input [1:0] IVAR;
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input [1:0] IVAR;
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input IVAR_MUX;
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input [31:12] VADR_D;
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input [28:4] KOLLI_A;
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input [28:4] KOLLI_A;
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input [3:0] MCR_FLAGS;
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input [3:0] MCR_FLAGS;
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input [23:0] MMU_DIN;
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input [23:0] MMU_DIN;
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input [31:0] VADR;
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input [31:0] VADR_I;
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input INHIBIT;
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input INHIBIT;
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input ENA_HK;
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input ENA_HK;
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input ENDRAM;
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input ENDRAM;
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output IO_RD;
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output IO_RD;
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reg [31:0] DFFE_IOR;
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reg [31:0] DFFE_IOR;
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reg HOLD_ON;
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reg HOLD_ON;
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reg DFF_HDFF1;
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reg DFF_HDFF1;
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reg DFF_IRD_REG;
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reg DFF_IRD_REG;
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wire [31:0] VADR;
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wire [4:0] A_CV;
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wire [4:0] A_CV;
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wire ACOK;
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wire ACOK;
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wire [4:0] ACV;
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wire [4:0] ACV;
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wire AUX_DAT;
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wire AUX_DAT;
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wire CA_HIT;
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wire CA_HIT;
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assign LD_DRAM_A = ~DRAM_ACC | MDONE;
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assign LD_DRAM_A = ~DRAM_ACC | MDONE;
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assign ICTODC[3] = USER;
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assign ICTODC[3] = USER;
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assign VADR[31:12] = IVAR_MUX ? VADR_D : VADR_I[31:12];
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assign VADR[11:0] = VADR_I[11:0];
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always @(posedge BCLK) VADR_R <= VADR;
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always @(posedge BCLK) VADR_R <= VADR;
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always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
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always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
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always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
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always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
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