| Line 34... |
Line 34... |
//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. KOLDETECT Collision Detection Unit
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// 1. KOLDETECT Collision Detection Unit
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// 2. ICACHE_SM Instruction Cache State Machine
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// 2. ICACHE_SM Instruction Cache State Machine
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 1. KOLDETECT Collision Detection Unit
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// 1. KOLDETECT Collision Detection Unit
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module KOLDETECT ( BCLK, BRESET, DRAM_WR, CVALID, ADDR, TAG0, TAG1 , CFG , C_VALID, READ_I, ACC_OK,
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module KOLDETECT ( BCLK, BRESET, DRAM_WR, CVALID, ADDR, TAG0, TAG1 , CFG , C_VALID, READ_I, ACC_OK, HOLD, KDET, INVAL_A, ENA_HK,
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NEWCVAL, KOLLISION, STOP_ICRD, RUN_ICRD, KILL, KILLADR, ICTODC, STOP_CINV );
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NEWCVAL, KOLLISION, STOP_ICRD, RUN_ICRD, KILL, KILLADR, ICTODC, STOP_CINV );
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input BCLK;
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input BCLK;
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input BRESET;
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input BRESET;
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input DRAM_WR;
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input DRAM_WR;
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| Line 94... |
Line 94... |
wire [7:0] new_0,new_1;
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wire [7:0] new_0,new_1;
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wire dma_mode,ic_dma;
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wire dma_mode,ic_dma;
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wire free,ende;
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wire free,ende;
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wire init_b;
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wire init_b;
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always @(posedge BCLK) do_koll <= DRAM_WR & CFG[0]; // one cycle pulse, without Cache Enable no col
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always @(posedge BCLK) do_koll <= DRAM_WR & CFG[0]; // one cycle pulse, without Cache Enable no collision
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always @(posedge BCLK) addr_r <= ADDR;
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always @(posedge BCLK) addr_r <= ADDR;
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// similar logic like in CA_MATCH
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// similar logic like in CA_MATCH
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assign set_0 = C_VALID[7:0];
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assign set_0 = C_VALID[7:0];
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| Line 156... |
Line 156... |
2'b00 : fifo_c = adrfifo[35:27];
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2'b00 : fifo_c = adrfifo[35:27];
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endcase
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endcase
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// Control
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// Control
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assign last_match = counter[2] & (fifo_c == {addr_r[11:4],found_1}); // if Match with last Entry no
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assign last_match = counter[2] & (fifo_c == {addr_r[11:4],found_1}); // if Match with last Entry no new Entry
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assign wr_entry = kolli & ~last_match;
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assign wr_entry = kolli & ~last_match;
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always @(posedge BCLK)
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always @(posedge BCLK)
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casex ({init_b,wr_entry,do_kill,counter})
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casex ({init_b,wr_entry,do_kill,counter})
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6'b0_xx_xxx : counter <= 3'b000;
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6'b0_xx_xxx : counter <= 3'b000;
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6'b1_00_xxx : counter <= counter;
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6'b1_00_xxx : counter <= counter;
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6'b1_11_xxx : counter <= counter;
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6'b1_11_xxx : counter <= counter;
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6'b1_10_000 : counter <= 3'b100;
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6'b1_10_000 : counter <= 3'b100;
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6'b1_10_1xx : counter <= (counter[1:0] == 2'b11) ? 3'b111 : {counter[2],(counter[1:0] + 2'b01)};
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6'b1_10_1xx : counter <= (counter[1:0] == 2'b11) ? 3'b111 : {counter[2],(counter[1:0] + 2'b01)}; // Overflow avoid
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6'b1_01_1xx : counter <= (counter[1:0] == 2'b00) ? 3'b000 : {counter[2],(counter[1:0] + 2'b11)};
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6'b1_01_1xx : counter <= (counter[1:0] == 2'b00) ? 3'b000 : {counter[2],(counter[1:0] + 2'b11)};
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default : counter <= counter;
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default : counter <= counter;
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endcase
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endcase
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// DMA Access
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// DMA Access
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| Line 208... |
Line 208... |
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always @(posedge BCLK) pipe <= STOP_ICRD;
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always @(posedge BCLK) pipe <= STOP_ICRD;
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assign RUN_ICRD = ~(STOP_ICRD | pipe); // Release for IC_READ
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assign RUN_ICRD = ~(STOP_ICRD | pipe); // Release for IC_READ
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always @(posedge BCLK) do_kill <= STOP_ICRD & ~dma_mode & ~do_kill; // Write pulse in Cache Valid R
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always @(posedge BCLK) do_kill <= STOP_ICRD & ~dma_mode & ~do_kill; // Write pulse in Cache Valid RAM, 1 cycle on, 1 cycle off
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assign KILL = do_kill | (KDET & dma_kolli);
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assign KILL = do_kill | (KDET & dma_kolli);
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// Valid Daten prepare : different sources for DMA and DCACHE Kohaerenz
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// Valid Daten prepare : different sources for DMA and DCACHE Kohaerenz
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| Line 241... |
Line 241... |
// multiple signals are needed in DCACHE :
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// multiple signals are needed in DCACHE :
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assign ICTODC = {dma,ic_dma,~(counter[2:1] == 2'b11)};
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assign ICTODC = {dma,ic_dma,~(counter[2:1] == 2'b11)};
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endmodule
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endmodule
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. ICACHE_SM Instruction Cache State Machine
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// 2. ICACHE_SM Instruction Cache State Machine
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,
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module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,
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USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,
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USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,
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DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );
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DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );
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input BCLK;
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input BCLK;
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| Line 326... |
Line 326... |
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assign CUPDATE = card_flag & USE_CA & MDONE; // USE_CA = ~CI & ~LDC;
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assign CUPDATE = card_flag & USE_CA & MDONE; // USE_CA = ~CI & ~LDC;
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always @(posedge BCLK) rd_rdy <= card_flag & MDONE;
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always @(posedge BCLK) rd_rdy <= card_flag & MDONE;
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// The cache RAM can not provide fast enough the data after an Update. In this case a secondary dat
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// The cache RAM can not provide fast enough the data after an Update. In this case a secondary data path is activated
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assign AUX_DAT = rd_rdy;
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assign AUX_DAT = rd_rdy;
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// DRAM Interface :
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// DRAM Interface :
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always @(posedge BCLK) if (dram_go) DRAM_ACC <= 1'b1;
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always @(posedge BCLK) if (dram_go) DRAM_ACC <= 1'b1;
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| Line 341... |
Line 341... |
always @(posedge BCLK)
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always @(posedge BCLK)
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begin
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begin
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if (IO_ACC) IO_RD <= READ; else IO_RD <= IO_RD & ~IO_READY & BRESET;
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if (IO_ACC) IO_RD <= READ; else IO_RD <= IO_RD & ~IO_READY & BRESET;
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end
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end
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assign io_busy = IO_RD | rd_done; // access is gone in next clock cycle, therefore blocked with "rd
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assign io_busy = IO_RD | rd_done; // access is gone in next clock cycle, therefore blocked with "rd_done"
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always @(posedge BCLK) rd_done <= READ & IO_READY; // For READ one clock later for data to come thr
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always @(posedge BCLK) rd_done <= READ & IO_READY; // For READ one clock later for data to come through
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// global feedback to opcode fetch unit : you can continue
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// global feedback to opcode fetch unit : you can continue
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assign ACC_OK = IO_SPACE ? rd_done : (READ & MMU_HIT & rd_ende);
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assign ACC_OK = IO_SPACE ? rd_done : (READ & MMU_HIT & rd_ende);
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