| Line 1... |
Line 1... |
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// This file is part of the M32632 project
|
// This file is part of the M32632 project
|
// http://opencores.org/project,m32632
|
// http://opencores.org/project,m32632
|
//
|
//
|
// Filename: ICACHE_SM.v
|
// Filename: ICACHE_SM.v
|
// Version: 2.0
|
// Version: 3.0
|
// History: 1.0 first release of 30 Mai 2015
|
// History: 1.0 first release of 30 Mai 2015
|
// Date: 14 August 2016
|
// Date: 2 December 2018
|
//
|
//
|
// Copyright (C) 2016 Udo Moeller
|
// Copyright (C) 2018 Udo Moeller
|
//
|
//
|
// This source file may be used and distributed without
|
// This source file may be used and distributed without
|
// restriction provided that this copyright statement is not
|
// restriction provided that this copyright statement is not
|
// removed from the file and that any derivative work contains
|
// removed from the file and that any derivative work contains
|
// the original copyright notice and the associated disclaimer.
|
// the original copyright notice and the associated disclaimer.
|
| Line 29... |
Line 29... |
//
|
//
|
// You should have received a copy of the GNU Lesser General
|
// You should have received a copy of the GNU Lesser General
|
// Public License along with this source; if not, download it
|
// Public License along with this source; if not, download it
|
// from http://www.opencores.org/lgpl.shtml
|
// from http://www.opencores.org/lgpl.shtml
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// Modules contained in this file:
|
// Modules contained in this file:
|
// 1. KOLDETECT Collision Detection Unit
|
// 1. KOLDETECT Collision Detection Unit
|
// 2. ICACHE_SM Instruction Cache State Machine
|
// 2. DMUX Data Multiplexor
|
|
// 3. ICACHE_SM Instruction Cache State Machine
|
//
|
//
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
| Line 49... |
Line 50... |
|
|
input BCLK;
|
input BCLK;
|
input BRESET;
|
input BRESET;
|
input DRAM_WR;
|
input DRAM_WR;
|
input [23:0] CVALID; // Data from master Valid RAM
|
input [23:0] CVALID; // Data from master Valid RAM
|
input [27:4] ADDR;
|
input [28:4] ADDR;
|
input [27:12] TAG0,TAG1;
|
input [28:12] TAG0,TAG1;
|
input [1:0] CFG;
|
input [1:0] CFG;
|
input [23:0] C_VALID; // Data from secondary Valid RAM
|
input [23:0] C_VALID; // Data from secondary Valid RAM
|
input READ_I;
|
input READ_I;
|
input ACC_OK;
|
input ACC_OK;
|
input HOLD; // active low
|
input HOLD; // active low
|
| Line 69... |
Line 70... |
output KILL;
|
output KILL;
|
output [11:7] KILLADR;
|
output [11:7] KILLADR;
|
output [2:0] ICTODC;
|
output [2:0] ICTODC;
|
output STOP_CINV;
|
output STOP_CINV;
|
|
|
reg [27:4] addr_r;
|
reg [28:4] addr_r;
|
reg [7:0] clear;
|
reg [7:0] clear;
|
reg do_koll;
|
reg do_koll;
|
reg [2:0] counter;
|
reg [2:0] counter;
|
reg [1:0] wpointer,rpointer;
|
reg [1:0] wpointer,rpointer;
|
reg [35:0] adrfifo;
|
reg [35:0] adrfifo;
|
| Line 106... |
Line 107... |
assign set_1 = C_VALID[15:8];
|
assign set_1 = C_VALID[15:8];
|
|
|
assign valid_0 = set_0[addr_r[6:4]];
|
assign valid_0 = set_0[addr_r[6:4]];
|
assign valid_1 = set_1[addr_r[6:4]];
|
assign valid_1 = set_1[addr_r[6:4]];
|
|
|
assign match_0 = ( TAG0 == addr_r[27:12] ); // 4KB
|
assign match_0 = ( TAG0 == addr_r[28:12] ); // 4KB
|
assign match_1 = ( TAG1 == addr_r[27:12] ); // 4KB
|
assign match_1 = ( TAG1 == addr_r[28:12] ); // 4KB
|
|
|
assign found_0 = valid_0 & match_0;
|
assign found_0 = valid_0 & match_0;
|
assign found_1 = valid_1 & match_1;
|
assign found_1 = valid_1 & match_1;
|
|
|
assign kolli = (found_0 | found_1) & ~CFG[1] & do_koll; // Action only if ICACHE is not locked
|
assign kolli = (found_0 | found_1) & ~CFG[1] & do_koll; // Action only if ICACHE is not locked
|
| Line 244... |
Line 245... |
|
|
endmodule
|
endmodule
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 2. ICACHE_SM Instruction Cache State Machine
|
// 2. DMUX Data Multiplexor
|
|
//
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
module DMUX ( DRAM_Q, ADDR, CAP_Q );
|
|
|
|
input [127:0] DRAM_Q;
|
|
input [3:2] ADDR;
|
|
|
|
output reg [31:0] CAP_Q;
|
|
|
|
always @(ADDR or DRAM_Q)
|
|
case (ADDR)
|
|
2'b00 : CAP_Q = DRAM_Q[31:0];
|
|
2'b01 : CAP_Q = DRAM_Q[63:32];
|
|
2'b10 : CAP_Q = DRAM_Q[95:64];
|
|
2'b11 : CAP_Q = DRAM_Q[127:96];
|
|
endcase
|
|
|
|
endmodule
|
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
//
|
|
// 3. ICACHE_SM Instruction Cache State Machine
|
//
|
//
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,
|
module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,
|
USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,
|
USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,
|
DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );
|
DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );
|
