| Line 39... |
Line 39... |
// 4. SHIFTER Barrel Shifter for all Shift Opcodes
|
// 4. SHIFTER Barrel Shifter for all Shift Opcodes
|
// 5. FFS_LOGIK Logic for FFS opcode
|
// 5. FFS_LOGIK Logic for FFS opcode
|
// 6. SCHALE Enclosure for Adder/Subtractor
|
// 6. SCHALE Enclosure for Adder/Subtractor
|
// 7. I_PFAD The Integer Datapath
|
// 7. I_PFAD The Integer Datapath
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 1. BITMASK Mask Generator , was a ROM on falling edge in early days
|
// 1. BITMASK Mask Generator , was a ROM on falling edge in early days
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module BITMASK (AA, DOUT);
|
module BITMASK (AA, DOUT);
|
|
|
// 0 : FFFFFFFF; Masktype 1 , Zero from right
|
// 0 : FFFFFFFF; Masktype 1 , Zero from right
|
// 1 : FFFFFFFE;
|
// 1 : FFFFFFFE;
|
// 2 : FFFFFFFC;
|
// 2 : FFFFFFFC;
|
| Line 106... |
Line 106... |
2'b11 : DOUT = { dec_bit,{24{low}}};
|
2'b11 : DOUT = { dec_bit,{24{low}}};
|
endcase
|
endcase
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 2. MULFILTER Filter for Multiplier Input Data
|
// 2. MULFILTER Filter for Multiplier Input Data
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module MULFILTER (BWD, FLOAT, SRC1, SRC2, DEST1, DEST2);
|
module MULFILTER (BWD, FLOAT, SRC1, SRC2, DEST1, DEST2);
|
|
|
input [1:0] BWD;
|
input [1:0] BWD;
|
input FLOAT;
|
input FLOAT;
|
input [31:0] SRC1,SRC2;
|
input [31:0] SRC1,SRC2;
|
| Line 147... |
Line 147... |
default : DEST2 = SRC2;
|
default : DEST2 = SRC2;
|
endcase
|
endcase
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 3. SIGNMUL Signed Multiplier for Integer Multiplication
|
// 3. SIGNMUL Signed Multiplier for Integer Multiplication
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module SIGNMUL (dataa, datab, result);
|
module SIGNMUL (dataa, datab, result);
|
|
|
input signed [31:0] dataa,datab;
|
input signed [31:0] dataa,datab;
|
output signed [63:0] result;
|
output signed [63:0] result;
|
|
|
assign result = dataa * datab;
|
assign result = dataa * datab;
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 4. SHIFTER Barrel Shifter for all Shift Opcodes
|
// 4. SHIFTER Barrel Shifter for all Shift Opcodes
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module SHIFTER ( MASKE,ROT,LSH,ASH,SIZE,SH_VAL,SH_DAT,SH_OUT,MASK_SEL);
|
module SHIFTER ( MASKE,ROT,LSH,ASH,SIZE,SH_VAL,SH_DAT,SH_OUT,MASK_SEL);
|
|
|
input [31:0] MASKE;
|
input [31:0] MASKE;
|
input ROT,LSH,ASH;
|
input ROT,LSH,ASH;
|
input [1:0] SIZE;
|
input [1:0] SIZE;
|
| Line 199... |
Line 199... |
|
|
assign shift = (ROT & (SIZE == 2'b00)) ? {2'b11,SH_VAL[2:0]} : SH_VAL[4:0];
|
assign shift = (ROT & (SIZE == 2'b00)) ? {2'b11,SH_VAL[2:0]} : SH_VAL[4:0];
|
|
|
// Rotation logic
|
// Rotation logic
|
|
|
assign sh_dat_0 = shift[0] ? {sh_dat_in[30:0],sh_dat_in[31]} : sh_dat_in; // Rotation of 1 bit posi
|
assign sh_dat_0 = shift[0] ? {sh_dat_in[30:0],sh_dat_in[31]} : sh_dat_in; // Rotation of 1 bit position
|
assign sh_dat_1 = shift[1] ? {sh_dat_0[29:0],sh_dat_0[31:30]} : sh_dat_0; // 2
|
assign sh_dat_1 = shift[1] ? {sh_dat_0[29:0],sh_dat_0[31:30]} : sh_dat_0; // 2
|
assign sh_dat_2 = shift[2] ? {sh_dat_1[27:0],sh_dat_1[31:28]} : sh_dat_1; // 4
|
assign sh_dat_2 = shift[2] ? {sh_dat_1[27:0],sh_dat_1[31:28]} : sh_dat_1; // 4
|
assign sh_dat_3 = shift[3] ? {sh_dat_2[23:0],sh_dat_2[31:24]} : sh_dat_2; // 8
|
assign sh_dat_3 = shift[3] ? {sh_dat_2[23:0],sh_dat_2[31:24]} : sh_dat_2; // 8
|
assign sh_dat_4 = shift[4] ? {sh_dat_3[15:0],sh_dat_3[31:16]} : sh_dat_3; // 16
|
assign sh_dat_4 = shift[4] ? {sh_dat_3[15:0],sh_dat_3[31:16]} : sh_dat_3; // 16
|
|
|
| Line 236... |
Line 236... |
default : SH_OUT = sh_dat_4; // ROT
|
default : SH_OUT = sh_dat_4; // ROT
|
endcase
|
endcase
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 5. FFS_LOGIK Logic for FFS opcode
|
// 5. FFS_LOGIK Logic for FFS opcode
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module FFS_LOGIK (SRC1, SRC2, BWD, FLAG, DOUT);
|
module FFS_LOGIK (SRC1, SRC2, BWD, FLAG, DOUT);
|
|
|
input [31:0] SRC1;
|
input [31:0] SRC1;
|
input [4:0] SRC2;
|
input [4:0] SRC2;
|
input [1:0] BWD;
|
input [1:0] BWD;
|
| Line 315... |
Line 315... |
|
|
assign DOUT = FLAG ? 5'h0 : obits;
|
assign DOUT = FLAG ? 5'h0 : obits;
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 6. SCHALE Enclosure for Adder/Subtractor
|
// 6. SCHALE Enclosure for Adder/Subtractor
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module SCHALE (dataa, datab, cin, add_sub, bwd, result, cout, overflow);
|
module SCHALE (dataa, datab, cin, add_sub, bwd, result, cout, overflow);
|
|
|
input [31:0] dataa,datab;
|
input [31:0] dataa,datab;
|
input cin;
|
input cin;
|
input add_sub; // 1 = Addition , 0 = Subtraction
|
input add_sub; // 1 = Addition , 0 = Subtraction
|
| Line 357... |
Line 357... |
assign cout = add_sub ? summe[32] : ~summe[32];
|
assign cout = add_sub ? summe[32] : ~summe[32];
|
assign result = summe[31:0];
|
assign result = summe[31:0];
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 7. I_PFAD The Integer Datapath
|
// 7. I_PFAD The Integer Datapath
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module I_PFAD ( BCLK, BRESET, SFP_DAT, FSR, DP_OUT, SRC1, SRC2, BMASKE, ADDR, MRESULT, OPCODE, BWD,
|
module I_PFAD ( BCLK, BRESET, SFP_DAT, FSR, DP_OUT, SRC1, SRC2, BMASKE, ADDR, MRESULT, OPCODE, BWD, FL, SP_CMP, DP_CMP, LD_OUT,
|
WREN, WRADR, RDAA, DETOIP, BITSEL, OVF_BCD, DISP, RWVFLAG, DSR, I_OUT, PSR, BMCODE, OV_FLAG, ACB
|
WREN, WRADR, RDAA, DETOIP, BITSEL, OVF_BCD, DISP, RWVFLAG, DSR, I_OUT, PSR, BMCODE, OV_FLAG, ACB_ZERO, STRING);
|
|
|
input BCLK,BRESET;
|
input BCLK,BRESET;
|
input [31:0] SFP_DAT,FSR,DP_OUT;
|
input [31:0] SFP_DAT,FSR,DP_OUT;
|
input [31:0] SRC1,SRC2;
|
input [31:0] SRC1,SRC2;
|
input [31:0] BMASKE;
|
input [31:0] BMASKE;
|
| Line 403... |
Line 403... |
reg [31:0] bwd_daten1,bwd_daten2;
|
reg [31:0] bwd_daten1,bwd_daten2;
|
wire [31:0] addsub_q;
|
wire [31:0] addsub_q;
|
|
|
// +++++++++++++ Global Output Multiplexer ++++++++++++++++++++++++++++
|
// +++++++++++++ Global Output Multiplexer ++++++++++++++++++++++++++++
|
|
|
always @(OPCODE or pfad_4 or pfad_5 or pfad_6 or pfad_7 or pfad_8 or DP_OUT or FL or SFP_DAT or FSR
|
always @(OPCODE or pfad_4 or pfad_5 or pfad_6 or pfad_7 or pfad_8 or DP_OUT or FL or SFP_DAT or FSR or pfad_11)
|
casex (OPCODE[7:3])
|
casex (OPCODE[7:3])
|
5'b0100_x : I_OUT = pfad_4;
|
5'b0100_x : I_OUT = pfad_4;
|
5'b0101_x : I_OUT = pfad_5; // String opcodes
|
5'b0101_x : I_OUT = pfad_5; // String opcodes
|
5'b0110_x : I_OUT = pfad_6;
|
5'b0110_x : I_OUT = pfad_6;
|
5'b0111_x : I_OUT = pfad_7;
|
5'b0111_x : I_OUT = pfad_7;
|
| Line 438... |
Line 438... |
wire ffs_flag; // FLAG result of FFS
|
wire ffs_flag; // FLAG result of FFS
|
wire chk_flag; // FLAG result of CHECK
|
wire chk_flag; // FLAG result of CHECK
|
wire save_psr,pop_psr;
|
wire save_psr,pop_psr;
|
wire [4:0] selbits;
|
wire [4:0] selbits;
|
// Bits from DETOIP;
|
// Bits from DETOIP;
|
wire cmps_op,ph_match,until,kill_opt,inss_op,exin_cmd,extract,bit_reg,kurz_st,dw_info,acb_reg,t2p
|
wire cmps_op,ph_match,until,kill_opt,inss_op,exin_cmd,extract,bit_reg,kurz_st,dw_info,acb_reg,t2p;
|
wire bcd_op,bcd_carry;
|
wire bcd_op,bcd_carry;
|
|
|
assign cmps_op = DETOIP[11]; // for CMPS
|
assign cmps_op = DETOIP[11]; // for CMPS
|
assign ph_match = DETOIP[10]; // MATCH phase
|
assign ph_match = DETOIP[10]; // MATCH phase
|
assign until = DETOIP[9]; // UNITL Flag for String
|
assign until = DETOIP[9]; // UNITL Flag for String
|
| Line 462... |
Line 462... |
assign ld_psr_l = ((WRADR == 6'h1D) | (WRADR == 6'h10)) & WREN; // Register PSR & UPSR
|
assign ld_psr_l = ((WRADR == 6'h1D) | (WRADR == 6'h10)) & WREN; // Register PSR & UPSR
|
assign ld_psr_h = (WRADR == 6'h1D) & (BWD != 2'b00) & WREN; // Register PSR
|
assign ld_psr_h = (WRADR == 6'h1D) & (BWD != 2'b00) & WREN; // Register PSR
|
// LD_OUT[1] is coming out of DECODER for this purpose
|
// LD_OUT[1] is coming out of DECODER for this purpose
|
assign up_psr = bcd_op | ((cmp_op | bit_op | ari_op | neg_op | ffs_op | chk_op) & LD_OUT);
|
assign up_psr = bcd_op | ((cmp_op | bit_op | ari_op | neg_op | ffs_op | chk_op) & LD_OUT);
|
|
|
assign cmp_op = (OPCODE == 8'h41) | ((OPCODE == 8'hB2) & (FL ? ~SP_CMP[2] : ~DP_CMP[2])); // CMPi o
|
assign cmp_op = (OPCODE == 8'h41) | ((OPCODE == 8'hB2) & (FL ? ~SP_CMP[2] : ~DP_CMP[2])); // CMPi or (CMPf & ~NAN)
|
assign bit_op = ((OPCODE[7:4] == 4'h6) & ((~OPCODE[3] & OPCODE[1]) | OPCODE[3:0] == 4'hE)) // the
|
assign bit_op = ((OPCODE[7:4] == 4'h6) & ((~OPCODE[3] & OPCODE[1]) | OPCODE[3:0] == 4'hE)) // the last term is for IBIT
|
| (OPCODE == 8'h4D) | str_op | rwv_op; // TBIT or CMPS or RDVAL/WRVAL
|
| (OPCODE == 8'h4D) | str_op | rwv_op; // TBIT or CMPS or RDVAL/WRVAL
|
assign ari_op = (OPCODE[7:4] == 4'h4) & (OPCODE[1:0] == 2'b0) & ~dw_info; // ADDi,ADDCi,SUBi,SUBCi
|
assign ari_op = (OPCODE[7:4] == 4'h4) & (OPCODE[1:0] == 2'b0) & ~dw_info; // ADDi,ADDCi,SUBi,SUBCi - special case ADJSPi no flags
|
assign neg_op = (OPCODE[7:4] == 4'h6) & (OPCODE[3] & (OPCODE[1:0] == 2'b0)); // ABSi,NEGi
|
assign neg_op = (OPCODE[7:4] == 4'h6) & (OPCODE[3] & (OPCODE[1:0] == 2'b0)); // ABSi,NEGi
|
assign ffs_op = (OPCODE == 8'h85); // FFS
|
assign ffs_op = (OPCODE == 8'h85); // FFS
|
assign chk_op = (OPCODE == 8'h83); // CHECK
|
assign chk_op = (OPCODE == 8'h83); // CHECK
|
assign str_op = (OPCODE[7:4] == 4'h5) & (OPCODE[3:2] == 2'b0) & ~kurz_st; // String-"S" opcodes : F
|
assign str_op = (OPCODE[7:4] == 4'h5) & (OPCODE[3:2] == 2'b0) & ~kurz_st; // String-"S" opcodes : F-Flag to 0, at start always
|
assign abs_op = (OPCODE == 8'h6C); // ABSi : Carry is not affected !
|
assign abs_op = (OPCODE == 8'h6C); // ABSi : Carry is not affected !
|
assign rwv_op = (OPCODE[7:4] == 4'hE) & (OPCODE[3:1] == 3'b0); // RDVAL + WRVAL
|
assign rwv_op = (OPCODE[7:4] == 4'hE) & (OPCODE[3:1] == 3'b0); // RDVAL + WRVAL
|
|
|
always @(bwd_daten1 or bwd_daten2 or addsub_q) // SRC1 > SRC2 ?
|
always @(bwd_daten1 or bwd_daten2 or addsub_q) // SRC1 > SRC2 ?
|
case ({bwd_daten2[31],bwd_daten1[31]})
|
case ({bwd_daten2[31],bwd_daten1[31]})
|
| Line 482... |
Line 482... |
2'b10 : nl_int = { 1'b1 , 1'b0 };
|
2'b10 : nl_int = { 1'b1 , 1'b0 };
|
2'b11 : nl_int = {addsub_q[31],addsub_q[31]};
|
2'b11 : nl_int = {addsub_q[31],addsub_q[31]};
|
endcase
|
endcase
|
|
|
assign ACB_ZERO = (addsub_q == 32'h0); // is used for ACBi opcode too
|
assign ACB_ZERO = (addsub_q == 32'h0); // is used for ACBi opcode too
|
assign f_flag = str_op ? 1'b0 : (rwv_op ? RWVFLAG : (bit_op ? SRC2[selbits] : (acb_reg ? PSR[5] : o
|
assign f_flag = str_op ? 1'b0 : (rwv_op ? RWVFLAG : (bit_op ? SRC2[selbits] : (acb_reg ? PSR[5] : over_flow)));
|
assign fp_nz = FL ? SP_CMP[1:0] : DP_CMP[1:0];
|
assign fp_nz = FL ? SP_CMP[1:0] : DP_CMP[1:0];
|
assign z_flag = OPCODE[1] ? fp_nz[0] : ACB_ZERO;
|
assign z_flag = OPCODE[1] ? fp_nz[0] : ACB_ZERO;
|
assign nl_flags = OPCODE[1] ? {fp_nz[1],1'b0} : nl_int;
|
assign nl_flags = OPCODE[1] ? {fp_nz[1],1'b0} : nl_int;
|
|
|
always @(*) // Bits : N Z F V - L T C
|
always @(*) // Bits : N Z F V - L T C
|
casex ({cmp_op,bcd_op,bit_op,(ffs_op | chk_op)})
|
casex ({cmp_op,bcd_op,bit_op,(ffs_op | chk_op)})
|
4'b0000 : psr_new = {PSR[7:6], f_flag,PSR[4:1],((acb_reg | abs_op) ? PSR[0] : cy_out)};
|
4'b0000 : psr_new = {PSR[7:6], f_flag,PSR[4:1],((acb_reg | abs_op) ? PSR[0] : cy_out)}; // arithmetic Op : CY and F
|
4'b0001 : psr_new = {PSR[7:6],(ffs_op ? ffs_flag : chk_flag),PSR[4:0]}; // FFS or CHECK
|
4'b0001 : psr_new = {PSR[7:6],(ffs_op ? ffs_flag : chk_flag),PSR[4:0]}; // FFS or CHECK
|
4'b001x : psr_new = (cmps_op & str_op) ?
|
4'b001x : psr_new = (cmps_op & str_op) ?
|
{2'b01, f_flag,PSR[4:3],1'b0,PSR[1:0]} // Init CMPS
|
{2'b01, f_flag,PSR[4:3],1'b0,PSR[1:0]} // Init CMPS
|
: {PSR[7:6], f_flag,PSR[4:0]}; // Bit opcode
|
: {PSR[7:6], f_flag,PSR[4:0]}; // Bit opcode
|
4'b01xx : psr_new = {PSR[7:6], 1'b0, PSR[4:1],bcd_carry}; // BCD opcode
|
4'b01xx : psr_new = {PSR[7:6], 1'b0, PSR[4:1],bcd_carry}; // BCD opcode
|
| Line 502... |
Line 502... |
: {nl_flags[1],z_flag,PSR[5:3], nl_flags[0],PSR[1:0]}; // CMP f or i
|
: {nl_flags[1],z_flag,PSR[5:3], nl_flags[0],PSR[1:0]}; // CMP f or i
|
endcase
|
endcase
|
|
|
always @(save_psr or pop_psr or OPCODE or PSR or SRC1)
|
always @(save_psr or pop_psr or OPCODE or PSR or SRC1)
|
casex ({save_psr,pop_psr,OPCODE[6],OPCODE[2]})
|
casex ({save_psr,pop_psr,OPCODE[6],OPCODE[2]})
|
4'b10xx : calc_psr = PSR & {~OPCODE[0],11'h0ED}; // clear P S U V T and the I-Bit at Interrupt &
|
4'b10xx : calc_psr = PSR & {~OPCODE[0],11'h0ED}; // clear P S U V T and the I-Bit at Interrupt & ABORT
|
4'b11xx : calc_psr = SRC1[27:16];
|
4'b11xx : calc_psr = SRC1[27:16];
|
4'b0x00 : calc_psr = PSR & ~SRC1[11:0]; // BICPSR : Opcode = h32
|
4'b0x00 : calc_psr = PSR & ~SRC1[11:0]; // BICPSR : Opcode = h32
|
4'b0x01 : calc_psr = PSR | SRC1[11:0]; // BISPSR h36
|
4'b0x01 : calc_psr = PSR | SRC1[11:0]; // BISPSR h36
|
default : calc_psr = SRC1[11:0]; // LPR PSR h76
|
default : calc_psr = SRC1[11:0]; // LPR PSR h76
|
endcase
|
endcase
|
| Line 532... |
Line 532... |
else // t2p : copy T-Bit into P-Bit at the beginning of opcode
|
else // t2p : copy T-Bit into P-Bit at the beginning of opcode
|
if (t2p) psr_high <= {psr_high[3],psr_low[1],psr_high[1:0]};
|
if (t2p) psr_high <= {psr_high[3],psr_low[1],psr_high[1:0]};
|
end
|
end
|
|
|
// Register for storage of PSR at Entry of Exception
|
// Register for storage of PSR at Entry of Exception
|
always @(posedge BCLK) if (save_psr) push_psr <= {PSR[11],(~OPCODE[1] & PSR[10]),PSR[9:0]}; // P-Fl
|
always @(posedge BCLK) if (save_psr) push_psr <= {PSR[11],(~OPCODE[1] & PSR[10]),PSR[9:0]}; // P-Flag modified
|
|
|
assign PSR = {psr_high,psr_low};
|
assign PSR = {psr_high,psr_low};
|
|
|
// ++++++++++++++ Overflow Detection ++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++ Overflow Detection ++++++++++++++++++++++++++++++++++++++
|
|
|
| Line 581... |
Line 581... |
2'b00 : bwd_daten1 = {{24{SRC1[7]}}, SRC1[7:0]}; // Sign Extension
|
2'b00 : bwd_daten1 = {{24{SRC1[7]}}, SRC1[7:0]}; // Sign Extension
|
2'b01 : bwd_daten1 = {{16{SRC1[15]}},SRC1[15:0]};
|
2'b01 : bwd_daten1 = {{16{SRC1[15]}},SRC1[15:0]};
|
default : bwd_daten1 = SRC1;
|
default : bwd_daten1 = SRC1;
|
endcase
|
endcase
|
|
|
assign add_flag = ~OPCODE[3] & ~OPCODE[1] & ~OPCODE[0]; // Only ADDi and ADDCi otherwise subtract i
|
assign add_flag = ~OPCODE[3] & ~OPCODE[1] & ~OPCODE[0]; // Only ADDi and ADDCi otherwise subtract in SCHALE
|
|
|
always @(PSR or OPCODE) // more effort due to ABSi und NEGi : Format 6
|
always @(PSR or OPCODE) // more effort due to ABSi und NEGi : Format 6
|
casex ({OPCODE[5],OPCODE[3:2]})
|
casex ({OPCODE[5],OPCODE[3:2]})
|
3'b000 : cy_in = OPCODE[0]; // ADD + CMP
|
3'b000 : cy_in = OPCODE[0]; // ADD + CMP
|
3'b001 : cy_in = PSR[0]; // ADDC
|
3'b001 : cy_in = PSR[0]; // ADDC
|
3'b011 : cy_in = ~PSR[0]; // SUBC
|
3'b011 : cy_in = ~PSR[0]; // SUBC
|
default : cy_in = 1'b1; // SUB + ABS + NEG : BORROW must be 1 for normal Adder
|
default : cy_in = 1'b1; // SUB + ABS + NEG : BORROW must be 1 for normal Adder
|
endcase
|
endcase
|
|
|
SCHALE addsub_ipfad (.dataa(bwd_daten2), .datab(bwd_daten1), .cin(cy_in), .add_sub(add_flag),
|
SCHALE addsub_ipfad (.dataa(bwd_daten2), .datab(bwd_daten1), .cin(cy_in), .add_sub(add_flag), .bwd(BWD),
|
.result(addsub_q), .cout(cy_out), .overflow(over_flow) );
|
.result(addsub_q), .cout(cy_out), .overflow(over_flow) );
|
|
|
always @(posedge BCLK) get_psr <= (RDAA == 8'h9D) | (RDAA == 8'h90) | (RDAA == 8'h93); // PSR or US
|
always @(posedge BCLK) get_psr <= (RDAA == 8'h9D) | (RDAA == 8'h90) | (RDAA == 8'h93); // PSR or US or DSR is read
|
always @(posedge BCLK) rd_psr <= (RDAA[1:0] == 2'b01);
|
always @(posedge BCLK) rd_psr <= (RDAA[1:0] == 2'b01);
|
always @(posedge BCLK) rd_dsr <= (RDAA[1:0] == 2'b11);
|
always @(posedge BCLK) rd_dsr <= (RDAA[1:0] == 2'b11);
|
|
|
always @(OPCODE or SRC1 or SRC2 or get_psr or rd_psr or rd_dsr or DSR or PSR or ADDR)
|
always @(OPCODE or SRC1 or SRC2 or get_psr or rd_psr or rd_dsr or DSR or PSR or ADDR)
|
casex (OPCODE[3:1])
|
casex (OPCODE[3:1])
|
3'b001 : pfad_4a = SRC2 & ~SRC1; // BIC
|
3'b001 : pfad_4a = SRC2 & ~SRC1; // BIC
|
3'bx10 : pfad_4a = get_psr ? {({4{rd_dsr}} & DSR),16'd0,({4{rd_psr}} & PSR[11:8]),({8{~rd_dsr}}
|
3'bx10 : pfad_4a = get_psr ? {({4{rd_dsr}} & DSR),16'd0,({4{rd_psr}} & PSR[11:8]),({8{~rd_dsr}} & PSR[7:0])} : SRC1; // MOV
|
3'b011 : pfad_4a = SRC2 | SRC1; // OR
|
3'b011 : pfad_4a = SRC2 | SRC1; // OR
|
3'b101 : pfad_4a = SRC2 & SRC1; // AND
|
3'b101 : pfad_4a = SRC2 & SRC1; // AND
|
3'b111 : pfad_4a = SRC2 ^ SRC1; // XOR
|
3'b111 : pfad_4a = SRC2 ^ SRC1; // XOR
|
default : pfad_4a = ADDR; // ADDR, comes from ADDR_UNIT
|
default : pfad_4a = ADDR; // ADDR, comes from ADDR_UNIT
|
endcase
|
endcase
|
| Line 620... |
Line 620... |
wire [3:0] abzug;
|
wire [3:0] abzug;
|
wire mehr,weiter,op_str,no_opt;
|
wire mehr,weiter,op_str,no_opt;
|
|
|
assign op_str = (OPCODE[7:3] == 5'b0101_0);
|
assign op_str = (OPCODE[7:3] == 5'b0101_0);
|
|
|
// This logic is for detection if an accelerated MOVS/MOVM inside a page is possible - Backward is
|
// This logic is for detection if an accelerated MOVS/MOVM inside a page is possible - Backward is not possible
|
always @(posedge BCLK)
|
always @(posedge BCLK)
|
if (op_str)
|
if (op_str)
|
begin
|
begin
|
spointer <= OPCODE[2] ? SRC1[11:0] : (spointer + {8'h00,todo[3:0]}); // Source
|
spointer <= OPCODE[2] ? SRC1[11:0] : (spointer + {8'h00,todo[3:0]}); // Source
|
dpointer <= OPCODE[2] ? SRC2[11:0] : (dpointer + {8'h00,todo[3:0]}); // Destination
|
dpointer <= OPCODE[2] ? SRC2[11:0] : (dpointer + {8'h00,todo[3:0]}); // Destination
|
| Line 667... |
Line 667... |
|
|
always @(posedge BCLK) if (op_str) todo_reg <= todo[9:4]; // store for next phase 51
|
always @(posedge BCLK) if (op_str) todo_reg <= todo[9:4]; // store for next phase 51
|
|
|
assign weiter = mehr | (pfad_5[3:0] != 4'h0);
|
assign weiter = mehr | (pfad_5[3:0] != 4'h0);
|
|
|
assign STRING = {1'b0,ACB_ZERO,weiter,( op_str ? todo[9:8] : todo_reg[9:8] )}; // ACB_ZERO is delay
|
assign STRING = {1'b0,ACB_ZERO,weiter,( op_str ? todo[9:8] : todo_reg[9:8] )}; // ACB_ZERO is delayed 1 cycle extern
|
|
|
// +++++++++++++ Format 6 opcodes : ADDP + SUBP are done in DP_FPU ++++++++++++++++++++
|
// +++++++++++++ Format 6 opcodes : ADDP + SUBP are done in DP_FPU ++++++++++++++++++++
|
|
|
wire rot,ash,lsh,eis_op;
|
wire rot,ash,lsh,eis_op;
|
wire [7:0] sh_count;
|
wire [7:0] sh_count;
|
| Line 683... |
Line 683... |
wire [4:0] shval_ei;
|
wire [4:0] shval_ei;
|
wire [7:0] sh_exin;
|
wire [7:0] sh_exin;
|
|
|
assign rot = (OPCODE[3:0] == 4'h0);
|
assign rot = (OPCODE[3:0] == 4'h0);
|
assign ash = (OPCODE[3:0] == 4'h1);
|
assign ash = (OPCODE[3:0] == 4'h1);
|
assign lsh = (OPCODE[3:1] == 3'b010); // 5 is LSH , but 4 is Trap(UND) and is used for right-shift
|
assign lsh = (OPCODE[3:1] == 3'b010); // 5 is LSH , but 4 is Trap(UND) and is used for right-shift of Offset !
|
|
|
assign eis_op = (OPCODE == 8'h73) | (OPCODE[7] & ~OPCODE[1] & inss_op); // EXTSi | INSSi at OPCODE=
|
assign eis_op = (OPCODE == 8'h73) | (OPCODE[7] & ~OPCODE[1] & inss_op); // EXTSi | INSSi at OPCODE=80h
|
assign exin_op = exin_cmd & (OPCODE[7:4] == 4'h8); // identifies EXT/INS
|
assign exin_op = exin_cmd & (OPCODE[7:4] == 4'h8); // identifies EXT/INS
|
assign exin_op2 = (exin_cmd | inss_op) & (OPCODE[7:4] == 4'h6); // identifies LSH
|
assign exin_op2 = (exin_cmd | inss_op) & (OPCODE[7:4] == 4'h6); // identifies LSH
|
|
|
always @(posedge BCLK) disp_reg <= DISP; // at EXT the path via ADDR is already used for DEST !!!
|
always @(posedge BCLK) disp_reg <= DISP; // at EXT the path via ADDR is already used for DEST !!!
|
always @(posedge BCLK) if (OPCODE[7]) offs_reg <= SRC1[7:5]; // for INSS , OPCODE=80h
|
always @(posedge BCLK) if (OPCODE[7]) offs_reg <= SRC1[7:5]; // for INSS , OPCODE=80h
|
|
|
// Byte for external Bit source, Double for Register
|
// Byte for external Bit source, Double for Register
|
assign selbits = (bit_reg | eis_op | exin_op) ? (exin_op ? disp_reg : SRC1[4:0]) : {2'b00,BITSEL};
|
assign selbits = (bit_reg | eis_op | exin_op) ? (exin_op ? disp_reg : SRC1[4:0]) : {2'b00,BITSEL};
|
|
|
assign shval_ei = inss_op ? {2'b00,offs_reg} : (bit_reg ? SRC1[4:0] : {2'b00,SRC1[2:0]});
|
assign shval_ei = inss_op ? {2'b00,offs_reg} : (bit_reg ? SRC1[4:0] : {2'b00,SRC1[2:0]});
|
assign sh_exin[4:0] = extract ? (5'd0 - shval_ei) : shval_ei; // EXT : right shift, INS : left shi
|
assign sh_exin[4:0] = extract ? (5'd0 - shval_ei) : shval_ei; // EXT : right shift, INS : left shift
|
assign sh_exin[7:5] = (shval_ei == 5'd0) ? 3'b000 : {3{extract}}; // Special case : 0 has no negati
|
assign sh_exin[7:5] = (shval_ei == 5'd0) ? 3'b000 : {3{extract}}; // Special case : 0 has no negativ sign !
|
|
|
// LSH shift by 16 bit to right
|
// LSH shift by 16 bit to right
|
assign sh_count = (OPCODE[3:0] == 4'h4) ? 8'hF0 : (exin_op2 ? sh_exin : SRC1[7:0]);
|
assign sh_count = (OPCODE[3:0] == 4'h4) ? 8'hF0 : (exin_op2 ? sh_exin : SRC1[7:0]);
|
|
|
assign BMCODE = (bit_op | eis_op | exin_op) ? {(eis_op | exin_op),(bit_op | exin_op),selbits} : {2'
|
assign BMCODE = (bit_op | eis_op | exin_op) ? {(eis_op | exin_op),(bit_op | exin_op),selbits} : {2'b00,shcode};
|
|
|
SHIFTER shift_inst (.MASKE(BMASKE), .ROT(rot), .ASH(ash), .LSH(lsh), .SH_DAT(SRC2), .SH_VAL(sh_cou
|
SHIFTER shift_inst (.MASKE(BMASKE), .ROT(rot), .ASH(ash), .LSH(lsh), .SH_DAT(SRC2), .SH_VAL(sh_count),
|
.MASK_SEL(shcode), .SIZE(BWD), .SH_OUT(shdat) );
|
.MASK_SEL(shcode), .SIZE(BWD), .SH_OUT(shdat) );
|
|
|
always @(BWD or SRC2 or neg_op or dw_info)
|
always @(BWD or SRC2 or neg_op or dw_info)
|
casex ({neg_op,(dw_info | BWD[1]),BWD[0]}) // special case ADJSPi
|
casex ({neg_op,(dw_info | BWD[1]),BWD[0]}) // special case ADJSPi
|
3'b000 : bwd_daten2 = {{24{SRC2[7]}}, SRC2[7:0]}; // Sign Extension
|
3'b000 : bwd_daten2 = {{24{SRC2[7]}}, SRC2[7:0]}; // Sign Extension
|
| Line 823... |
Line 823... |
|
|
always @(posedge BCLK) ins_maske <= shdat; // expensive solution in terms of LEs !
|
always @(posedge BCLK) ins_maske <= shdat; // expensive solution in terms of LEs !
|
|
|
always @(*)
|
always @(*)
|
casex (OPCODE[3:0]) // CVTP (81) has no OPCODE !
|
casex (OPCODE[3:0]) // CVTP (81) has no OPCODE !
|
4'b000x : pfad_8 = (extract ? SRC2 : 32'hFFFF_FFFF) & BMASKE; // EXT, the other form is for INS
|
4'b000x : pfad_8 = (extract ? SRC2 : 32'hFFFF_FFFF) & BMASKE; // EXT, the other form is for INS to get the mask
|
4'b0010 : pfad_8 = (SRC1 & ins_maske) | (SRC2 & ~ins_maske); // INS ins_maske[] ? SRC1[] : SRC2[
|
4'b0010 : pfad_8 = (SRC1 & ins_maske) | (SRC2 & ~ins_maske); // INS ins_maske[] ? SRC1[] : SRC2[]
|
4'b0011 : pfad_8 = BWD[1] ? addsub_q : {16'h0,chk_low};
|
4'b0011 : pfad_8 = BWD[1] ? addsub_q : {16'h0,chk_low};
|
4'b0101 : pfad_8 = {24'hxx_xxxx,3'b000,ffs_out};
|
4'b0101 : pfad_8 = {24'hxx_xxxx,3'b000,ffs_out};
|
default : pfad_8 = {4'hx,push_psr,SRC1[15:0]}; // Opcode x'87-x'8F is used at CXP and therefore
|
default : pfad_8 = {4'hx,push_psr,SRC1[15:0]}; // Opcode x'87-x'8F is used at CXP and therefore in Exception-Processing
|
endcase
|
endcase
|
|
|
// ++++++++++++++ Format 11 : Floating-Point Datapath +++++++++++++++++++++++++++++++
|
// ++++++++++++++ Format 11 : Floating-Point Datapath +++++++++++++++++++++++++++++++
|
|
|
assign pfad_11 = (OPCODE[1:0] == 2'b01) ?
|
assign pfad_11 = (OPCODE[1:0] == 2'b01) ?
|
