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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: I_PFAD.v
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// Filename: I_PFAD.v
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// Version: 1.0
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// Version: 1.1 bug fix
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 7 November 2015
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2015 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// ++++++++++++++ Format 5 Opcodes : Strings MOVS , CMPS und SKPS +++++++++++++++++++++++++++++++
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// ++++++++++++++ Format 5 Opcodes : Strings MOVS , CMPS und SKPS +++++++++++++++++++++++++++++++
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reg [11:0] spointer,dpointer;
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reg [11:0] spointer,dpointer;
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reg [9:0] todo;
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reg [9:0] todo;
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reg [9:4] todo_reg;
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reg [9:4] todo_reg;
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wire [3:0] abzug;
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reg dis_opt;
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wire [31:0] diff_poi;
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wire mehr,weiter,op_str,no_opt;
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wire mehr,weiter,op_str,no_opt;
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assign op_str = (OPCODE[7:3] == 5'b0101_0);
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assign op_str = (OPCODE[7:3] == 5'b0101_0);
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assign diff_poi = SRC2 - SRC1; // Special Case
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always @(posedge BCLK) if (op_str && OPCODE[2]) dis_opt <= (diff_poi[31:3] == 29'd0);
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// This logic is for detection if an accelerated MOVS/MOVM inside a page is possible - Backward is not possible
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// This logic is for detection if an accelerated MOVS/MOVM inside a page is possible - Backward is not possible
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (op_str)
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if (op_str)
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begin
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begin
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spointer <= OPCODE[2] ? SRC1[11:0] : (spointer + {8'h00,todo[3:0]}); // Source
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spointer <= OPCODE[2] ? SRC1[11:0] : (spointer + {8'h00,todo[3:0]}); // Source
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dpointer <= OPCODE[2] ? SRC2[11:0] : (dpointer + {8'h00,todo[3:0]}); // Destination
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dpointer <= OPCODE[2] ? SRC2[11:0] : (dpointer + {8'h00,todo[3:0]}); // Destination
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end
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end
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assign no_opt = OPCODE[1] | ((spointer[11:3] == 9'h1FF) & (spointer[2:0] != 3'b000))
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assign no_opt = OPCODE[1] | ((spointer[11:3] == 9'h1FF) & (spointer[2:0] != 3'b000))
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| kill_opt | ((dpointer[11:3] == 9'h1FF) & (dpointer[2:0] != 3'b000));
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| kill_opt | ((dpointer[11:3] == 9'h1FF) & (dpointer[2:0] != 3'b000))
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| dis_opt;
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assign abzug = OPCODE[0] ? todo_reg[7:4] : 4'h0 ;
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assign pfad_5 = SRC1 - {28'h0,abzug};
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assign pfad_5 = SRC1 - {28'h0,todo_reg[7:4]};
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assign mehr = (pfad_5[31:4] != 28'h0);
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assign mehr = (pfad_5[31:4] != 28'h0);
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always @(no_opt or BWD or mehr or pfad_5)
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always @(no_opt or BWD or mehr or pfad_5)
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casex ({no_opt,BWD,mehr,pfad_5[3:0]})
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casex ({no_opt,BWD,mehr,pfad_5[3:0]})
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8'b101_xxxxx : todo = 10'h112;
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8'b101_xxxxx : todo = 10'h112;
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8'b11x_xxxxx : todo = 10'h214;
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8'b11x_xxxxx : todo = 10'h214;
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default : todo = 10'hxxx;
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default : todo = 10'hxxx;
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endcase
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endcase
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always @(posedge BCLK) if (op_str) todo_reg <= todo[9:4]; // store for next phase 51
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always @(posedge BCLK) if (op_str) todo_reg <= {todo[9:8],(OPCODE[2] ? 4'd0 : todo[7:4])}; // store for next phase 51
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assign weiter = mehr | (pfad_5[3:0] != 4'h0);
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assign weiter = mehr | (pfad_5[3:0] != 4'h0);
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assign STRING = {1'b0,ACB_ZERO,weiter,( op_str ? todo[9:8] : todo_reg[9:8] )}; // ACB_ZERO is delayed 1 cycle extern
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assign STRING = {1'b0,ACB_ZERO,weiter,( op_str ? todo[9:8] : todo_reg[9:8] )}; // ACB_ZERO is delayed 1 cycle extern
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