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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: I_PFAD.v
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// Filename: I_PFAD.v
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// Version: 1.2 bug fix
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// Version: 2.0
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// Version: 1.1 bug fix release of 7 November 2015
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// History: 1.1 bug fix of 7 November 2015
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// History: 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 4 February 2016
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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input [1:0] BWD;
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input [1:0] BWD;
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input FLOAT;
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input FLOAT;
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input [31:0] SRC1,SRC2;
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input [31:0] SRC1,SRC2;
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output [31:0] DEST1,DEST2;
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output [31:0] DEST1,DEST2;
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wire sign1,sign2;
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reg [31:0] DEST1,DEST2;
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reg [31:0] DEST1,DEST2;
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assign sign1 = BWD[0] ? SRC1[15] : SRC1[7];
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always @(FLOAT or BWD or SRC1)
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casex ({FLOAT,BWD})
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always @(FLOAT or BWD or SRC1 or sign1)
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3'b0_00 : DEST1 = {{24{SRC1[7]}}, SRC1[7:0]};
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casex ({FLOAT,BWD,sign1})
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3'b0_01 : DEST1 = {{16{SRC1[15]}},SRC1[15:0]};
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4'b0_00_0 : DEST1 = {24'h000000, SRC1[7:0]};
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3'b1_xx : DEST1 = { 9'h001,SRC1[22:0]};
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4'b0_00_1 : DEST1 = {24'hFFFFFF, SRC1[7:0]};
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4'b0_01_0 : DEST1 = { 16'h0000,SRC1[15:0]};
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4'b0_01_1 : DEST1 = { 16'hFFFF,SRC1[15:0]};
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4'b1_xx_x : DEST1 = { 9'h001,SRC1[22:0]};
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default : DEST1 = SRC1;
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default : DEST1 = SRC1;
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endcase
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endcase
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assign sign2 = BWD[0] ? SRC2[15] : SRC2[7];
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always @(FLOAT or BWD or SRC2)
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casex ({FLOAT,BWD})
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always @(FLOAT or BWD or SRC2 or sign2)
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3'b0_00 : DEST2 = {{24{SRC2[7]}}, SRC2[7:0]};
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casex ({FLOAT,BWD,sign2})
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3'b0_01 : DEST2 = {{16{SRC2[15]}},SRC2[15:0]};
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4'b0_00_0 : DEST2 = {24'h000000, SRC2[7:0]};
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3'b1_xx : DEST2 = { 9'h001,SRC2[22:0]};
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4'b0_00_1 : DEST2 = {24'hFFFFFF, SRC2[7:0]};
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4'b0_01_0 : DEST2 = { 16'h0000,SRC2[15:0]};
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4'b0_01_1 : DEST2 = { 16'hFFFF,SRC2[15:0]};
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4'b1_xx_x : DEST2 = { 9'h001,SRC2[22:0]};
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default : DEST2 = SRC2;
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default : DEST2 = SRC2;
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endcase
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endcase
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endmodule
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endmodule
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wire [7:0] byte_0,byte_3;
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wire [7:0] byte_0,byte_3;
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wire [15:0] mdat_0;
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wire [15:0] mdat_0;
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wire [7:0] mdat_1;
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wire [7:0] mdat_1;
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wire [3:0] mdat_2;
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wire [3:0] mdat_2;
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wire [1:0] mdat_3;
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wire [4:0] obits;
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wire [4:0] obits;
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always @(*)
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always @(*)
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case (SRC2[2:0])
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case (SRC2[2:0])
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3'd0 : maske = 7'h7F;
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3'd0 : maske = 7'h7F;
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assign mdat_1 = obits[3] ? mdat_0[15:8] : mdat_0[7:0];
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assign mdat_1 = obits[3] ? mdat_0[15:8] : mdat_0[7:0];
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assign obits[2] = (mdat_1[3:0] == 4'h0);
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assign obits[2] = (mdat_1[3:0] == 4'h0);
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assign mdat_2 = obits[2] ? mdat_1[7:4] : mdat_1[3:0];
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assign mdat_2 = obits[2] ? mdat_1[7:4] : mdat_1[3:0];
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assign obits[1] = (mdat_2[1:0] == 2'b0);
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assign obits[1] = (mdat_2[1:0] == 2'b00);
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assign mdat_3 = obits[1] ? mdat_2[3:2] : mdat_2[1:0];
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assign obits[0] = ~((mdat_2[2:1] == 2'b10) | mdat_2[0]);
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assign obits[0] = ~mdat_3[0];
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always @(BWD or obits or mdat_3)
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always @(BWD or obits or mdat_2)
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casex ({BWD,obits[4:3]})
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casex ({BWD,obits[4:3]})
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4'b00_x1 : FLAG = 1; // Byte Overflow => nothing found
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4'b00_x1 : FLAG = 1; // Byte Overflow => nothing found
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4'b00_10 : FLAG = 1; // Byte Overflow => nothing found
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4'b00_10 : FLAG = 1; // Byte Overflow => nothing found
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4'b01_1x : FLAG = 1; // Word Overflow => nothing found
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4'b01_1x : FLAG = 1; // Word Overflow => nothing found
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default : FLAG = (mdat_3 == 2'b00);
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default : FLAG = (mdat_2 == 4'b0000);
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endcase
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endcase
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assign DOUT = FLAG ? 5'h0 : obits;
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assign DOUT = FLAG ? 5'h0 : obits;
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endmodule
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endmodule
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// Byte for external Bit source, Double for Register
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// Byte for external Bit source, Double for Register
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assign selbits = (bit_reg | eis_op | exin_op) ? (exin_op ? disp_reg : SRC1[4:0]) : {2'b00,BITSEL};
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assign selbits = (bit_reg | eis_op | exin_op) ? (exin_op ? disp_reg : SRC1[4:0]) : {2'b00,BITSEL};
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assign shval_ei = inss_op ? {2'b00,offs_reg} : (bit_reg ? SRC1[4:0] : {2'b00,SRC1[2:0]});
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assign shval_ei = inss_op ? {2'b00,offs_reg} : (bit_reg ? SRC1[4:0] : {2'b00,SRC1[2:0]});
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assign sh_exin[4:0] = extract ? (5'd0 - shval_ei) : shval_ei; // EXT : right shift, INS : left shift
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assign sh_exin[4:0] = ({5{extract}} ^ shval_ei) + {4'd0,extract}; // EXT : right shift, INS : left shift
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assign sh_exin[7:5] = (shval_ei == 5'd0) ? 3'b000 : {3{extract}}; // Special case : 0 has no negativ sign !
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assign sh_exin[7:5] = (shval_ei == 5'd0) ? 3'b000 : {3{extract}}; // Special case : 0 has no negativ sign !
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// LSH shift by 16 bit to right
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// LSH shift by 16 bit to right
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assign sh_count = (OPCODE[3:0] == 4'h4) ? 8'hF0 : (exin_op2 ? sh_exin : SRC1[7:0]);
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assign sh_count = (OPCODE[3:0] == 4'h4) ? 8'hF0 : (exin_op2 ? sh_exin : SRC1[7:0]);
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4'b1000 : pfad_6 = addsub_q; // NEG
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4'b1000 : pfad_6 = addsub_q; // NEG
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4'b1001 : pfad_6 = {SRC1[31:1],~SRC1[0]}; // NOT
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4'b1001 : pfad_6 = {SRC1[31:1],~SRC1[0]}; // NOT
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4'b1010 : pfad_6 = SRC1; // Special case 6A : not used normal -> op_lmr !
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4'b1010 : pfad_6 = SRC1; // Special case 6A : not used normal -> op_lmr !
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4'b1100 : pfad_6 = bwd_daten1[31] ? addsub_q : SRC1; // ABS
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4'b1100 : pfad_6 = bwd_daten1[31] ? addsub_q : SRC1; // ABS
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4'b1101 : pfad_6 = ~SRC1; // COM
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4'b1101 : pfad_6 = ~SRC1; // COM
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4'b1110 : pfad_6 = SRC2 ^ BMASKE; // IBIT
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4'b111x : pfad_6 = SRC2 ^ BMASKE; // IBIT
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4'b1x11_: pfad_6 = DP_OUT; // ADDP + SUBP
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default : pfad_6 = shdat; // Result of Barrelshifter
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default : pfad_6 = shdat; // Result of Barrelshifter
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endcase
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endcase
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// ++++++++++++++ Format 7 : MUL +++++++++++++++++++++++
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// ++++++++++++++ Format 7 : MUL +++++++++++++++++++++++
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