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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: I_PFAD.v
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// Filename: I_PFAD.v
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// Version: 2.0
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// Version: 3.0
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// History: 1.1 bug fix of 7 November 2015
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// History: 1.1 bug fix of 7 November 2015
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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// Date: 2 December 2018
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. BITMASK Mask Generator , was a ROM on falling edge in early days
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// 1. BITMASK Mask Generator , was a ROM on falling edge in early days
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// 2. MULFILTER Filter for Multiplier Input Data
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// 2. MULFILTER Filter for Multiplier Input Data
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// 3. SIGNMUL Signed Multiplier for Integer Multiplication
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// 3. SHIFTER Barrel Shifter for all Shift Opcodes
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// 4. SHIFTER Barrel Shifter for all Shift Opcodes
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// 4. FFS_LOGIK Logic for FFS opcode
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// 5. FFS_LOGIK Logic for FFS opcode
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// 5. SCHALE Enclosure for Adder/Subtractor
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// 6. SCHALE Enclosure for Adder/Subtractor
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// 6. I_PFAD The Integer Datapath
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// 7. I_PFAD The Integer Datapath
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. MULFILTER Filter for Multiplier Input Data
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// 2. MULFILTER Filter for Multiplier Input Data
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module MULFILTER (BWD, FLOAT, SRC1, SRC2, DEST1, DEST2);
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module MULFILTER (BWD, SRC1, SRC2, MRESULT);
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input [1:0] BWD;
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input [1:0] BWD;
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input FLOAT;
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input signed [31:0] SRC1,SRC2;
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input [31:0] SRC1,SRC2;
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output [32:0] MRESULT;
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output [31:0] DEST1,DEST2;
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reg [31:0] DEST1,DEST2;
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wire signed [63:0] muld;
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wire signed [31:0] mulw;
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always @(FLOAT or BWD or SRC1)
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wire no_ovf;
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casex ({FLOAT,BWD})
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3'b0_00 : DEST1 = {{24{SRC1[7]}}, SRC1[7:0]};
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3'b0_01 : DEST1 = {{16{SRC1[15]}},SRC1[15:0]};
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3'b1_xx : DEST1 = { 9'h001,SRC1[22:0]};
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default : DEST1 = SRC1;
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endcase
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always @(FLOAT or BWD or SRC2)
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casex ({FLOAT,BWD})
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3'b0_00 : DEST2 = {{24{SRC2[7]}}, SRC2[7:0]};
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3'b0_01 : DEST2 = {{16{SRC2[15]}},SRC2[15:0]};
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3'b1_xx : DEST2 = { 9'h001,SRC2[22:0]};
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default : DEST2 = SRC2;
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endcase
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endmodule
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assign muld = SRC1 * SRC2;
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assign mulw = {(BWD[0] ? SRC1[15:8] : {8{SRC1[7]}}),SRC1[7:0]} * {(BWD[0] ? SRC2[15:8] : {8{SRC2[7]}}),SRC2[7:0]};
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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assign no_ovf = BWD[1] ? (muld[63:32] == {32{muld[31]}})
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//
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: ( BWD[0] ? (mulw[31:16] == {16{mulw[15]}})
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// 3. SIGNMUL Signed Multiplier for Integer Multiplication
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: (mulw[15:8] == {8{mulw[7]}}) );
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SIGNMUL (dataa, datab, result);
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input signed [31:0] dataa,datab;
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output signed [63:0] result;
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assign result = dataa * datab;
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assign MRESULT = {~no_ovf,muld[31:16],(BWD[1] ? muld[15:0] : mulw[15:0])};
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 4. SHIFTER Barrel Shifter for all Shift Opcodes
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// 3. SHIFTER Barrel Shifter for all Shift Opcodes
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SHIFTER ( MASKE,ROT,LSH,ASH,SIZE,SH_VAL,SH_DAT,SH_OUT,MASK_SEL);
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module SHIFTER ( MASKE,ROT,LSH,ASH,SIZE,SH_VAL,SH_DAT,SH_OUT,MASK_SEL);
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input [31:0] MASKE;
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input [31:0] MASKE;
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 5. FFS_LOGIK Logic for FFS opcode
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// 4. FFS_LOGIK Logic for FFS opcode
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module FFS_LOGIK (SRC1, SRC2, BWD, FLAG, DOUT);
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module FFS_LOGIK (SRC1, SRC2, BWD, FLAG, DOUT);
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input [31:0] SRC1;
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input [31:0] SRC1;
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 6. SCHALE Enclosure for Adder/Subtractor
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// 5. SCHALE Enclosure for Adder/Subtractor
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SCHALE (dataa, datab, cin, add_sub, bwd, result, cout, overflow);
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module SCHALE (dataa, datab, cin, add_sub, bwd, result, cout, overflow);
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input [31:0] dataa,datab;
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input [31:0] dataa,datab;
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 7. I_PFAD The Integer Datapath
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// 6. I_PFAD The Integer Datapath
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module I_PFAD ( BCLK, BRESET, SFP_DAT, FSR, DP_OUT, SRC1, SRC2, BMASKE, ADDR, MRESULT, OPCODE, BWD, FL, SP_CMP, DP_CMP, LD_OUT,
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module I_PFAD ( BCLK, BRESET, SFP_DAT, FSR, DP_OUT, SRC1, SRC2, BMASKE, ADDR, MRESULT, OPCODE, BWD, FL, SP_CMP, DP_CMP, LD_OUT,
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WREN, WRADR, RDAA, DETOIP, BITSEL, OVF_BCD, DISP, RWVFLAG, DSR, I_OUT, PSR, BMCODE, OV_FLAG, ACB_ZERO, STRING);
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WREN, WRADR, RDAA, DETOIP, BITSEL, OVF_BCD, DISP, RWVFLAG, DSR, I_OUT, PSR, BMCODE, OV_FLAG, ACB_ZERO, STRING);
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input BCLK,BRESET;
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input BCLK,BRESET;
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input [31:0] SFP_DAT,FSR,DP_OUT;
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input [31:0] SFP_DAT,FSR,DP_OUT;
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input [31:0] SRC1,SRC2;
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input [31:0] SRC1,SRC2;
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input [31:0] BMASKE;
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input [31:0] BMASKE;
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input [31:0] ADDR;
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input [31:0] ADDR;
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input [63:0] MRESULT;
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input [32:0] MRESULT;
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input [7:0] OPCODE;
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input [7:0] OPCODE;
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input [1:0] BWD;
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input [1:0] BWD;
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input FL;
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input FL;
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input [2:0] SP_CMP;
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input [2:0] SP_CMP;
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input [2:0] DP_CMP;
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input [2:0] DP_CMP;
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assign PSR = {psr_high,psr_low};
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assign PSR = {psr_high,psr_low};
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// ++++++++++++++ Overflow Detection ++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++ Overflow Detection ++++++++++++++++++++++++++++++++++++++
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reg ovf_mul,ovf_ash;
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reg ovf_ash;
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wire [31:0] shdat;
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wire [31:0] shdat;
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) OV_FLAG <= 1'b0;
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if (!BRESET) OV_FLAG <= 1'b0;
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else
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else
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if (OVF_BCD[3]) OV_FLAG <= OVF_BCD[2]; // DEI,QUO,DIV
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if (OVF_BCD[3]) OV_FLAG <= OVF_BCD[2]; // DEI,QUO,DIV
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else
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else
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if (LD_OUT)
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if (LD_OUT)
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case (OPCODE)
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case (OPCODE)
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8'h78 : OV_FLAG <= ovf_mul;
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8'h78 : OV_FLAG <= MRESULT[32];
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8'h61 : OV_FLAG <= ovf_ash;
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8'h61 : OV_FLAG <= ovf_ash;
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8'h40 : OV_FLAG <= over_flow & acb_reg; // ADD Opcode at ACB
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8'h40 : OV_FLAG <= over_flow & acb_reg; // ADD Opcode at ACB
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default : OV_FLAG <= 1'b0;
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default : OV_FLAG <= 1'b0;
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endcase
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endcase
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always @(BWD or MRESULT)
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casex (BWD)
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2'b00 : ovf_mul = ~((MRESULT[15:7] == 9'd0) | (MRESULT[15:7] == 9'h1FF));
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2'b01 : ovf_mul = ~((MRESULT[31:15] == 17'd0) | (MRESULT[31:15] == 17'h1FFFF));
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default : ovf_mul = ~((MRESULT[63:31] == 33'd0) | (MRESULT[63:31] == 33'h1FFFFFFFF));
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endcase
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always @(BWD or SRC2 or shdat)
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always @(BWD or SRC2 or shdat)
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casex (BWD)
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casex (BWD)
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2'b00 : ovf_ash = (SRC2[7] != shdat[7]);
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2'b00 : ovf_ash = (SRC2[7] != shdat[7]);
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2'b01 : ovf_ash = (SRC2[15] != shdat[15]);
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2'b01 : ovf_ash = (SRC2[15] != shdat[15]);
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default : ovf_ash = (SRC2[31] != shdat[31]);
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default : ovf_ash = (SRC2[31] != shdat[31]);
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