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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: M32632.v
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// Filename: M32632.v
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// Version: 1.1 bug fix
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// Version: 2.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.1 bug fix of 7 October 2015
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// Date: 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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// Modules contained in this file:
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// Modules contained in this file:
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// M32632 The top level of M32632
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// M32632 The top level of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module M32632( BCLK, MCLK, WRCFG, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,
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module M32632( BCLK, MCLK, WRCFG, DRAMSZ, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,
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IO_WR, IO_RD, IO_A, IO_BE, IO_DI, IO_Q, IO_READY,
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IO_WR, IO_RD, IO_A, IO_BE, IO_DI, IO_Q, IO_READY,
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ENDRAM, IC_MDONE, DC_MDONE, ENWR, WAMUX, WADDR, DRAM_Q, DWCTRL, IWCTRL,
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ENDRAM, IC_MDONE, DC_MDONE, ENWR, WAMUX, WADDR, DRAM_Q, DWCTRL, IWCTRL,
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IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,
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IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,
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HOLD, HLDA, FILLRAM, DMA_AA,
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HOLD, HLDA, DMA_CHK, DMA_AA,
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COP_GO, COP_OP, COP_OUT, COP_DONE, COP_IN );
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COP_GO, COP_OP, COP_OUT, COP_DONE, COP_IN );
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// ++++++++++ Basic Signals
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// ++++++++++ Basic Signals
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input BCLK; // Basic Clock for everything
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input BCLK; // Basic Clock for everything
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input MCLK; // Memory Clock, used in Caches
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input MCLK; // Memory Clock, used in Caches
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input WRCFG;
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input WRCFG;
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input [2:0] DRAMSZ;
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input BRESET;
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input BRESET;
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input NMI_N;
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input NMI_N;
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input INT_N;
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input INT_N;
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output [3:0] STATUS;
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output [3:0] STATUS;
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output ILO;
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output ILO;
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output [27:0] DRAM_ADR;
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output [27:0] DRAM_ADR;
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output [35:0] DRAM_DI;
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output [35:0] DRAM_DI;
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// ++++++++++ DMA Interface
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// ++++++++++ DMA Interface
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input HOLD;
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input HOLD;
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output HLDA;
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output HLDA;
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input FILLRAM;
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input DMA_CHK;
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input [27:4] DMA_AA;
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input [27:4] DMA_AA;
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// ++++++++++ Coprocessor Interface
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// ++++++++++ Coprocessor Interface
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output COP_GO;
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output COP_GO;
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output [23:0] COP_OP;
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output [23:0] COP_OP;
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output [127:0] COP_OUT;
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output [127:0] COP_OUT;
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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DCACHE ARMS(
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DCACHE ARMS(
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.MCLK(MCLK),
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.MCLK(MCLK),
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.BCLK(BCLK),
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.BCLK(BCLK),
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.WRCFG(WRCFG),
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.WRCFG(WRCFG),
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.DRAMSZ(DRAMSZ),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.PTB_WR(PTB_WR),
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.PTB_WR(PTB_WR),
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.PTB_SEL(PTB_SEL),
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.PTB_SEL(PTB_SEL),
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.MDONE(DC_MDONE),
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.MDONE(DC_MDONE),
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.IO_READY(D_IORDY),
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.IO_READY(D_IORDY),
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.RMW(RMW),
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.RMW(RMW),
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.QWATWO(QWATWO),
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.QWATWO(QWATWO),
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.WAMUX(WAMUX),
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.WAMUX(WAMUX),
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.ENWR(ENWR),
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.ENWR(ENWR),
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.IC_PREQ(IC_PREQ),
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.IC_PREQ(IC_PREQ),
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.FILLRAM(FILLRAM),
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.DMA_CHK(DMA_CHK),
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.CFG(CFG[10:9]),
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.CFG(CFG[10:9]),
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.ENDRAM(ENDRAM),
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.ENDRAM(ENDRAM),
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.CINVAL(CINV[1:0]),
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.CINVAL(CINV[1:0]),
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.DMA_AA(DMA_AA),
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.DMA_AA(DMA_AA),
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.DP_Q(DP_Q),
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.DP_Q(DP_Q),
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// The Instruction Cache
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// The Instruction Cache
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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ICACHE LEGS(
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ICACHE LEGS(
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.MCLK(MCLK),
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.MCLK(MCLK),
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.BCLK(BCLK),
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.BCLK(BCLK),
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.DRAMSZ(DRAMSZ),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.PTB_WR(PTB_WR),
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.PTB_WR(PTB_WR),
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.PTB_SEL(PTB_SEL),
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.PTB_SEL(PTB_SEL),
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.MDONE(IC_MDONE),
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.MDONE(IC_MDONE),
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.IO_READY(I_IORDY),
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.IO_READY(I_IORDY),
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