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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
//
 
//
 
// This file is part of the M32632 project
 
// This file is part of the M32632 project
 
// http://opencores.org/project,m32632
 
// http://opencores.org/project,m32632
 
//
 
//
 
//      Filename:       M32632.v
 
//      Filename:       M32632.v
 
//      Version:        2.0
 
//  Version:    3.0 Cache Interface reworked
 
//      History:        1.1 bug fix of 7 October 2015
 
//      History:        2.1 bug fix of 26 November 2016
 
 
 
//                              2.0 50 MHz release of 14 August 2016
 
 
 
//                              1.1 bug fix of 7 October 2015
 
//                              1.0 first release of 30 Mai 2015
 
//                              1.0 first release of 30 Mai 2015
 
//      Date:           14 August 2016
 
//      Date:           2 December 2018
 
//
 
//
 
// Copyright (C) 2016 Udo Moeller
 
// Copyright (C) 2018 Udo Moeller
 
// 
// 
// This source file may be used and distributed without 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// restriction provided that this copyright statement is not 
// removed from the file and that any derivative work contains 
// removed from the file and that any derivative work contains 
// the original copyright notice and the associated disclaimer.
 
// the original copyright notice and the associated disclaimer.
Line 30... Line 32... 
// 
// 
// You should have received a copy of the GNU Lesser General 
// You should have received a copy of the GNU Lesser General 
// Public License along with this source; if not, download it 
// Public License along with this source; if not, download it 
// from http://www.opencores.org/lgpl.shtml 
// from http://www.opencores.org/lgpl.shtml 
// 
// 
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
//
 
//
 
//      Modules contained in this file:
 
//      Modules contained in this file:
 
//      M32632          The top level of M32632
 
//      M32632          The top level of M32632
 
//
 
//
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
 
 
 
 
module M32632( BCLK, MCLK, WRCFG, DRAMSZ, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,
 
module M32632( BCLK, DRAMSZ, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,
 
                           IO_WR, IO_RD, IO_A, IO_BE, IO_DI, IO_Q, IO_READY,
 
                           IO_WR, IO_RD, IO_A, IO_BE, IO_DI, IO_Q, IO_READY,
 
                           ENDRAM, IC_MDONE, DC_MDONE, ENWR, WAMUX, WADDR, DRAM_Q, DWCTRL, IWCTRL,
 
                           ENDRAM, IC_MDONE, DC_MDONE, ENWR, DRAM_Q, DC_INHIBIT, IC_INHIBIT,
 
                           IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,
 
                           IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,
 
                           HOLD, HLDA, DMA_CHK, DMA_AA,
 
                           HOLD, HLDA, DMA_CHK, DMA_AA,
 
                           COP_GO, COP_OP, COP_OUT, COP_DONE, COP_IN );
 
                           COP_GO, COP_OP, COP_OUT, COP_DONE, COP_IN );
 
 
 
 
 
// ++++++++++ Basic Signals
 
// ++++++++++ Basic Signals
 
input                   BCLK;   // Basic Clock for everything
 
input                   BCLK;   // Basic Clock for everything
 
input                   MCLK;   // Memory Clock, used in Caches
 
 
 
input                   WRCFG;
 
 
 
input    [2:0]   DRAMSZ;
 
input    [2:0]   DRAMSZ;
 
input                   BRESET;
 
input                   BRESET;
 
input                   NMI_N;
 
input                   NMI_N;
 
input                   INT_N;
 
input                   INT_N;
 
output   [3:0]   STATUS;
 
output   [3:0]   STATUS;
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// +++++++++ DRAM Interface In
 
// +++++++++ DRAM Interface In
 
input                   ENDRAM;
 
input                   ENDRAM;
 
input                   IC_MDONE;
 
input                   IC_MDONE;
 
input                   DC_MDONE;
 
input                   DC_MDONE;
 
input                   ENWR;
 
input                   ENWR;
 
input                   WAMUX;
 
input  [127:0]   DRAM_Q;
 
input   [11:2]  WADDR;
 
input                   DC_INHIBIT;
 
input   [31:0]   DRAM_Q;
 
input                   IC_INHIBIT;
 
input    [2:0]   DWCTRL;
 
 
 
input    [2:0]   IWCTRL;
 
 
 
// +++++++++ DRAM Interface Out
 
// +++++++++ DRAM Interface Out
 
output                  IC_ACC;
 
output                  IC_ACC;
 
output  [27:0]   IDRAM_ADR;
 
output  [28:0]   IDRAM_ADR;
 
output                  DC_ACC;
 
output                  DC_ACC;
 
output                  DC_WR;
 
output                  DC_WR;
 
output  [27:0]   DRAM_ADR;
 
output  [28:0]   DRAM_ADR;
 
output  [35:0]   DRAM_DI;
 
output  [35:0]   DRAM_DI;
 
// ++++++++++ DMA Interface
 
// ++++++++++ DMA Interface
 
input                   HOLD;
 
input                   HOLD;
 
output                  HLDA;
 
output                  HLDA;
 
input                   DMA_CHK;
 
input                   DMA_CHK;
 
input   [27:4]  DMA_AA;
 
input   [28:4]  DMA_AA;
 
// ++++++++++ Coprocessor Interface
 
// ++++++++++ Coprocessor Interface
 
output                  COP_GO;
 
output                  COP_GO;
 
output  [23:0]   COP_OP;
 
output  [23:0]   COP_OP;
 
output [127:0]   COP_OUT;
 
output [127:0]   COP_OUT;
 
input                   COP_DONE;
 
input                   COP_DONE;
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wire   [31:12]  IC_VA;
 
wire   [31:12]  IC_VA;
 
wire     [3:0]   ICTODC;
 
wire     [3:0]   ICTODC;
 
wire     [6:0]   INFO_AU;
 
wire     [6:0]   INFO_AU;
 
wire     [1:0]   IVAR;
 
wire     [1:0]   IVAR;
 
wire                    KDET;
 
wire                    KDET;
 
wire    [27:4]  KOLLI_A;
 
wire    [28:4]  KOLLI_A;
 
wire     [3:0]   MCR;
 
wire     [3:0]   MCR;
 
wire    [23:0]   MMU_DIN;
 
wire    [23:0]   MMU_DIN;
 
wire    [11:0]   PSR;
 
wire    [11:0]   PSR;
 
wire                    PTB_SEL;
 
wire                    PTB_SEL;
 
wire                    PTB_WR;
 
wire                    PTB_WR;
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wire                    QWATWO;
 
wire                    QWATWO;
 
wire     [2:0]   RWVAL;
 
wire     [2:0]   RWVAL;
 
wire                    RWVFLAG;
 
wire                    RWVFLAG;
 
wire     [3:0]   D_IOBE;
 
wire     [3:0]   D_IOBE;
 
wire                    D_IORDY;
 
wire                    D_IORDY;
 
wire                    REG_OUT;
 
wire     [1:0]   CTRL_QW;
 
wire     [3:0]   PACKET;
 
wire     [3:0]   PACKET;
 
wire     [1:0]   SIZE;
 
wire     [1:0]   SIZE;
 
wire    [31:0]   VADR;
 
wire    [31:0]   VADR;
 
wire                    WREN_REG;
 
wire                    WREN_REG;
 
wire                    LD_DIN;
 
wire                    LD_DIN;
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
//            The Data Cache
 
//            The Data Cache
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
DCACHE  ARMS(
 
DCACHE  ARMS(
 
        .MCLK(MCLK),
 
 
 
        .BCLK(BCLK),
 
        .BCLK(BCLK),
 
        .WRCFG(WRCFG),
 
 
 
        .DRAMSZ(DRAMSZ),
 
        .DRAMSZ(DRAMSZ),
 
        .BRESET(BRESET),
 
        .BRESET(BRESET),
 
        .PTB_WR(PTB_WR),
 
        .PTB_WR(PTB_WR),
 
        .PTB_SEL(PTB_SEL),
 
        .PTB_SEL(PTB_SEL),
 
        .MDONE(DC_MDONE),
 
        .MDONE(DC_MDONE),
 
        .IO_READY(D_IORDY),
 
        .IO_READY(D_IORDY),
 
        .REG_OUT(REG_OUT),
 
        .CTRL_QW(CTRL_QW),
 
        .PSR_USER(INFO_AU[1]),
 
        .PSR_USER(INFO_AU[1]),
 
        .WRITE(WRITE),
 
        .WRITE(WRITE),
 
        .READ(READ),
 
        .READ(READ),
 
        .ZTEST(ZTEST),
 
        .ZTEST(ZTEST),
 
        .RMW(RMW),
 
        .RMW(RMW),
 
        .QWATWO(QWATWO),
 
        .QWATWO(QWATWO),
 
        .WAMUX(WAMUX),
 
 
 
        .ENWR(ENWR),
 
        .ENWR(ENWR),
 
        .IC_PREQ(IC_PREQ),
 
        .IC_PREQ(IC_PREQ),
 
        .DMA_CHK(DMA_CHK),
 
        .DMA_CHK(DMA_CHK),
 
        .CFG(CFG[10:9]),
 
        .CFG(CFG[10:9]),
 
        .ENDRAM(ENDRAM),
 
        .ENDRAM(ENDRAM),
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        .IVAR(IVAR),
 
        .IVAR(IVAR),
 
        .MCR_FLAGS(MCR),
 
        .MCR_FLAGS(MCR),
 
        .PACKET(PACKET),
 
        .PACKET(PACKET),
 
        .SIZE(SIZE),
 
        .SIZE(SIZE),
 
        .VADR(VADR),
 
        .VADR(VADR),
 
        .WADDR(WADDR),
 
        .INHIBIT(DC_INHIBIT),
 
        .WCTRL(DWCTRL),
 
 
 
        .DRAM_ACC(DC_ACC),
 
        .DRAM_ACC(DC_ACC),
 
        .DRAM_WR(DC_WR),
 
        .DRAM_WR(DC_WR),
 
        .IO_RD(D_IORD),
 
        .IO_RD(D_IORD),
 
        .IO_WR(D_IOWR),
 
        .IO_WR(D_IOWR),
 
        .INIT_RUN(DC_INIT),
 
        .INIT_RUN(DC_INIT),
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        .WRITE_OUT(WRITE),
 
        .WRITE_OUT(WRITE),
 
        .ZTEST(ZTEST),
 
        .ZTEST(ZTEST),
 
        .RMW(RMW),
 
        .RMW(RMW),
 
        .QWATWO(QWATWO),
 
        .QWATWO(QWATWO),
 
        .ACC_DONE(ACC_DONE),
 
        .ACC_DONE(ACC_DONE),
 
        .REG_OUT(REG_OUT),
 
        .CTRL_QW(CTRL_QW),
 
        .Y_INIT(Y_INIT),
 
        .Y_INIT(Y_INIT),
 
        .DONE(DONE),
 
        .DONE(DONE),
 
        .PTB_WR(PTB_WR),
 
        .PTB_WR(PTB_WR),
 
        .PTB_SEL(PTB_SEL),
 
        .PTB_SEL(PTB_SEL),
 
        .ACB_ZERO(ACB_ZERO),
 
        .ACB_ZERO(ACB_ZERO),
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
//            The Instruction Cache
 
//            The Instruction Cache
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
ICACHE  LEGS(
 
ICACHE  LEGS(
 
        .MCLK(MCLK),
 
 
 
        .BCLK(BCLK),
 
        .BCLK(BCLK),
 
        .DRAMSZ(DRAMSZ),
 
        .DRAMSZ(DRAMSZ),
 
        .BRESET(BRESET),
 
        .BRESET(BRESET),
 
        .PTB_WR(PTB_WR),
 
        .PTB_WR(PTB_WR),
 
        .PTB_SEL(PTB_SEL),
 
        .PTB_SEL(PTB_SEL),
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        .IVAR(IVAR),
 
        .IVAR(IVAR),
 
        .KOLLI_A(KOLLI_A),
 
        .KOLLI_A(KOLLI_A),
 
        .MCR_FLAGS(MCR),
 
        .MCR_FLAGS(MCR),
 
        .MMU_DIN(MMU_DIN),
 
        .MMU_DIN(MMU_DIN),
 
        .VADR(PC_ICACHE),
 
        .VADR(PC_ICACHE),
 
        .WADDR(WADDR),
 
        .INHIBIT(IC_INHIBIT),
 
        .WCTRL(IWCTRL),
 
 
 
        .DRAM_ACC(IC_ACC),
 
        .DRAM_ACC(IC_ACC),
 
        .IO_RD(I_IORD),
 
        .IO_RD(I_IORD),
 
        .INIT_RUN(IC_INIT),
 
        .INIT_RUN(IC_INIT),
 
        .PROT_ERROR(PROT_ERROR),
 
        .PROT_ERROR(PROT_ERROR),
 
        .ACC_OK(IACC_STAT[0]),
 
        .ACC_OK(IACC_STAT[0]),

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