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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: REGISTERS.v
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// Filename: REGISTERS.v
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// Version: 3.0
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// Project: M32632
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// Version: 3.1 bug fix of 25 February 2019
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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// Author: Udo Moeller
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// Date: 8 July 2017
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//
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//
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// Copyright (C) 2018 Udo Moeller
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// Copyright (C) 2019 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// 1. CONFIG_REGS Configuration and Debug Registers
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// 1. CONFIG_REGS Configuration and Debug Registers
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
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module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
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CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
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CFG, MCR, PTB_WR, PTB_SEL, IVAR, IVAR_MUX, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input WREN,LD_OUT;
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input WREN,LD_OUT;
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input [7:0] OPCODE;
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input [7:0] OPCODE;
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input [31:0] SRC1;
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input [31:0] SRC1;
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output [12:0] CFG;
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output [12:0] CFG;
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output [3:0] MCR;
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output [3:0] MCR;
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output PTB_WR;
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output PTB_WR;
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output PTB_SEL;
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output PTB_SEL;
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output [1:0] IVAR;
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output [1:0] IVAR;
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output IVAR_MUX;
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output [3:0] CINV;
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output [3:0] CINV;
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output Y_INIT;
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output Y_INIT;
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output [3:0] DSR;
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output [3:0] DSR;
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output [2:0] DBG_TRAPS;
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output [2:0] DBG_TRAPS;
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output [40:2] DBG_IN;
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output [40:2] DBG_IN;
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) MCR <= 4'h0;
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if (!BRESET) MCR <= 4'h0;
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else if (ld_mcr) MCR <= SRC1[3:0];
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else if (ld_mcr) MCR <= SRC1[3:0];
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always @(posedge BCLK) ivarreg <= op_ok & (WRADR[5:1] == 5'd7) & WREN; // IVAR0/1 = Reg. Nr. 14/15
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assign IVAR_MUX = op_ok & (WRADR[5:1] == 5'd7) & WREN; // IVAR0/1 = Reg. Nr. 14/15
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always @(posedge BCLK) ivarreg <= IVAR_MUX;
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assign IVAR = {ivarreg,PTB_SEL};
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assign IVAR = {ivarreg,PTB_SEL};
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always @(posedge BCLK) PTB_WR <= op_ok & (WRADR[5:1] == 5'd6) & WREN; // PTB0/1 = Reg. Nr. 12/13
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always @(posedge BCLK) PTB_WR <= op_ok & (WRADR[5:1] == 5'd6) & WREN; // PTB0/1 = Reg. Nr. 12/13
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always @(posedge BCLK) PTB_SEL <= WRADR[0];
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always @(posedge BCLK) PTB_SEL <= WRADR[0];
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