| Line 35... |
Line 35... |
// Modules contained in this file:
|
// Modules contained in this file:
|
// 1. CONFIG_REGS Configuration and Debug Registers
|
// 1. CONFIG_REGS Configuration and Debug Registers
|
// 2. FP_STAT_REG Floating Point Status Register
|
// 2. FP_STAT_REG Floating Point Status Register
|
// 3. REGISTER General Purpose Registers
|
// 3. REGISTER General Purpose Registers
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 1. CONFIG_REGS Configuration and Debug Registers
|
// 1. CONFIG_REGS Configuration and Debug Registers
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_H
|
module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
|
CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
|
CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
|
|
|
input BCLK,BRESET;
|
input BCLK,BRESET;
|
input WREN,LD_OUT;
|
input WREN,LD_OUT;
|
input [7:0] OPCODE;
|
input [7:0] OPCODE;
|
| Line 103... |
Line 103... |
always @(posedge BCLK) PTB_SEL <= WRADR[0];
|
always @(posedge BCLK) PTB_SEL <= WRADR[0];
|
|
|
// The Cache content will be invalid if the Enable-Bit is set to 0
|
// The Cache content will be invalid if the Enable-Bit is set to 0
|
always @(posedge BCLK) old_cfg <= {CFG[11],CFG[9]};
|
always @(posedge BCLK) old_cfg <= {CFG[11],CFG[9]};
|
|
|
// Cache Invalidate : the Flags are coming out of the Short-field which is otherwise used for Regis
|
// Cache Invalidate : the Flags are coming out of the Short-field which is otherwise used for Register selection
|
always @(posedge BCLK) ci_all <= do_cinv & WRADR[2] ? WRADR[1:0] : 2'b0; // clear all
|
always @(posedge BCLK) ci_all <= do_cinv & WRADR[2] ? WRADR[1:0] : 2'b0; // clear all
|
always @(posedge BCLK) ci_line <= do_cinv & ~WRADR[2] ? WRADR[1:0] : 2'b0; // clear cache line
|
always @(posedge BCLK) ci_line <= do_cinv & ~WRADR[2] ? WRADR[1:0] : 2'b0; // clear cache line
|
|
|
assign init_ic = old_cfg[1] & (~CFG[11] | ci_all[1]);
|
assign init_ic = old_cfg[1] & (~CFG[11] | ci_all[1]);
|
assign init_dc = old_cfg[0] & (~CFG[9] | ci_all[0]);
|
assign init_dc = old_cfg[0] & (~CFG[9] | ci_all[0]);
|
| Line 143... |
Line 143... |
|
|
always @(posedge BCLK) if (ld_bpc) bpc <= SRC1;
|
always @(posedge BCLK) if (ld_bpc) bpc <= SRC1;
|
always @(posedge BCLK) if (ld_car) car <= SRC1[31:2];
|
always @(posedge BCLK) if (ld_car) car <= SRC1[31:2];
|
|
|
// DEN SD DEN UD CAE CRD CAE CWR VNP/CBE CAR
|
// DEN SD DEN UD CAE CRD CAE CWR VNP/CBE CAR
|
assign DBG_IN = {(dcr[12] & dcr[11]),(dcr[12] & dcr[10]),(dcr[7] & dcr[6]),(dcr[7] & dcr[5]),dcr[4:
|
assign DBG_IN = {(dcr[12] & dcr[11]),(dcr[12] & dcr[10]),(dcr[7] & dcr[6]),(dcr[7] & dcr[5]),dcr[4:0],car};
|
|
|
always @(posedge BCLK or negedge BRESET)
|
always @(posedge BCLK or negedge BRESET)
|
if (!BRESET) DSR <= 4'd0;
|
if (!BRESET) DSR <= 4'd0;
|
else
|
else
|
if (ld_dsr) DSR <= SRC1[31:28];
|
if (ld_dsr) DSR <= SRC1[31:28];
|
| Line 163... |
Line 163... |
assign DBG_TRAPS[1] = DBG_HIT; // Compare Adress Hit
|
assign DBG_TRAPS[1] = DBG_HIT; // Compare Adress Hit
|
assign DBG_TRAPS[2] = dcr[8]; // TR, Trap enable
|
assign DBG_TRAPS[2] = dcr[8]; // TR, Trap enable
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 2. FP_STAT_REG Floating Point Status Register
|
// 2. FP_STAT_REG Floating Point Status Register
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module FP_STAT_REG ( BCLK, BRESET, LFSR, UP_SP, UP_DP, TT_SP, TT_DP, WREN, WRADR, DIN, FSR, TWREN, F
|
module FP_STAT_REG ( BCLK, BRESET, LFSR, UP_SP, UP_DP, TT_SP, TT_DP, WREN, WRADR, DIN, FSR, TWREN, FPU_TRAP, SAVE_PC);
|
|
|
input BCLK;
|
input BCLK;
|
input BRESET;
|
input BRESET;
|
input LFSR; // Load by LFSR opcode
|
input LFSR; // Load by LFSR opcode
|
input UP_SP,UP_DP; // update if calculation operation
|
input UP_SP,UP_DP; // update if calculation operation
|
| Line 256... |
Line 256... |
|
|
assign SAVE_PC = (UP_SP | UP_DP) & ~FPU_TRAP; // Store the correct PC for FPU Trap
|
assign SAVE_PC = (UP_SP | UP_DP) & ~FPU_TRAP; // Store the correct PC for FPU Trap
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 3. REGISTER General Purpose Registers
|
// 3. REGISTER General Purpose Registers
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module REGISTER( BCLK, ENWR, DOWR, BYDIN, DIN, RADR, WADR, WMASKE, DOUT, SELI );
|
module REGISTER( BCLK, ENWR, DOWR, BYDIN, DIN, RADR, WADR, WMASKE, DOUT, SELI );
|
|
|
input BCLK;
|
input BCLK;
|
input DOWR,ENWR;
|
input DOWR,ENWR;
|
input [31:0] BYDIN,DIN;
|
input [31:0] BYDIN,DIN;
|
