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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: REGISTERS.v
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// Filename: REGISTERS.v
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// Version: 1.0
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// Version: 2.0
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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input [1:0] WMASKE;
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input [1:0] WMASKE;
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output [31:0] DOUT;
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output [31:0] DOUT;
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output reg SELI;
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output reg SELI;
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reg [2:0] MX;
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reg [2:0] mx;
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wire [3:0] BE;
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wire [2:0] be;
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wire eq_rw;
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wire eq_rw;
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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reg [7:0] REGFILE_D [0:63];
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reg [15:0] REGFILE_C [0:63]; // Byte 3 and 2 , Verilog allows no "Byte Write" in wider memories !!!
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reg [7:0] REGFILE_C [0:63];
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reg [7:0] REGFILE_B [0:63]; // Byte 1
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reg [7:0] REGFILE_B [0:63];
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reg [7:0] REGFILE_A [0:63]; // Byte 0
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reg [7:0] REGFILE_A [0:63];
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reg [31:0] RF;
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reg [31:0] RF;
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assign BE = {WMASKE[1],WMASKE[1],(WMASKE[1] | WMASKE[0]),1'b1};
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assign be = {WMASKE[1],(WMASKE[1] | WMASKE[0]),1'b1};
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assign eq_rw = ENWR & (RADR[5:0] == WADR);
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assign eq_rw = ENWR & (RADR[5:0] == WADR);
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always @(posedge BCLK) if (RADR[7]) MX[2:0] <= BE[2:0] & {{3{eq_rw}}};
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always @(posedge BCLK) if (RADR[7]) mx[2:0] <= be[2:0] & {{3{eq_rw}}};
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always @(posedge BCLK) if (RADR[7]) SELI <= RADR[6];
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always @(posedge BCLK) if (RADR[7]) SELI <= RADR[6];
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assign DOUT[31:16] = MX[2] ? BYDIN[31:16] : RF[31:16];
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assign DOUT[31:16] = mx[2] ? BYDIN[31:16] : RF[31:16];
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assign DOUT[15:8] = MX[1] ? BYDIN[15:8] : RF[15:8];
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assign DOUT[15:8] = mx[1] ? BYDIN[15:8] : RF[15:8];
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assign DOUT[7:0] = MX[0] ? BYDIN[7:0] : RF[7:0];
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assign DOUT[7:0] = mx[0] ? BYDIN[7:0] : RF[7:0];
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// ++++++++++++++++ Register File 64 * 32 Bits ++++++++++++
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// ++++++++++++++++ Register File 64 * 32 Bits ++++++++++++
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (RADR[7])
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if (RADR[7])
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begin
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begin
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RF[31:24] <= REGFILE_D[RADR[5:0]];
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RF[31:16] <= REGFILE_C[RADR[5:0]];
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RF[23:16] <= REGFILE_C[RADR[5:0]];
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RF[15:8] <= REGFILE_B[RADR[5:0]];
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RF[15:8] <= REGFILE_B[RADR[5:0]];
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RF[7:0] <= REGFILE_A[RADR[5:0]];
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RF[7:0] <= REGFILE_A[RADR[5:0]];
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end
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end
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (DOWR)
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if (DOWR)
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begin
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begin
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if (BE[3]) REGFILE_D[WADR] <= DIN[31:24];
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if (be[2]) REGFILE_C[WADR] <= DIN[31:16];
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if (BE[2]) REGFILE_C[WADR] <= DIN[23:16];
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if (be[1]) REGFILE_B[WADR] <= DIN[15:8];
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if (BE[1]) REGFILE_B[WADR] <= DIN[15:8];
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if (be[0]) REGFILE_A[WADR] <= DIN[7:0];
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if (BE[0]) REGFILE_A[WADR] <= DIN[7:0];
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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