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[/] [m32632/] [trunk/] [rtl/] [REGISTERS.v] - Diff between revs 29 and 48

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//
//
// This file is part of the M32632 project
// This file is part of the M32632 project
// http://opencores.org/project,m32632
// http://opencores.org/project,m32632
//
//
//      Filename:       REGISTERS.v
//      Filename:       REGISTERS.v
//      Version:        3.0
//      Project:        M32632
 
//  Version:    3.1 bug fix of 25 February 2019
//      History:        1.0 first release of 30 Mai 2015
//      History:        1.0 first release of 30 Mai 2015
//      Date:           2 December 2018
//      Author:         Udo Moeller
 
//      Date:           8 July 2017
//
//
// Copyright (C) 2018 Udo Moeller
// Copyright (C) 2019 Udo Moeller
// 
// 
// This source file may be used and distributed without 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// restriction provided that this copyright statement is not 
// removed from the file and that any derivative work contains 
// removed from the file and that any derivative work contains 
// the original copyright notice and the associated disclaimer.
// the original copyright notice and the associated disclaimer.
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//
//
//      1. CONFIG_REGS  Configuration and Debug Registers
//      1. CONFIG_REGS  Configuration and Debug Registers
//
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
                                         CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
                                         CFG, MCR, PTB_WR, PTB_SEL, IVAR, IVAR_MUX, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
 
 
        input                   BCLK,BRESET;
        input                   BCLK,BRESET;
        input                   WREN,LD_OUT;
        input                   WREN,LD_OUT;
        input    [7:0]   OPCODE;
        input    [7:0]   OPCODE;
        input   [31:0]   SRC1;
        input   [31:0]   SRC1;
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        output  [12:0]   CFG;
        output  [12:0]   CFG;
        output   [3:0]   MCR;
        output   [3:0]   MCR;
        output                  PTB_WR;
        output                  PTB_WR;
        output                  PTB_SEL;
        output                  PTB_SEL;
        output   [1:0]   IVAR;
        output   [1:0]   IVAR;
 
        output                  IVAR_MUX;
        output   [3:0]   CINV;
        output   [3:0]   CINV;
        output                  Y_INIT;
        output                  Y_INIT;
        output   [3:0]   DSR;
        output   [3:0]   DSR;
        output   [2:0]   DBG_TRAPS;
        output   [2:0]   DBG_TRAPS;
        output  [40:2]  DBG_IN;
        output  [40:2]  DBG_IN;
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        always @(posedge BCLK or negedge BRESET)
        always @(posedge BCLK or negedge BRESET)
                if (!BRESET) MCR <= 4'h0;
                if (!BRESET) MCR <= 4'h0;
                        else if (ld_mcr) MCR <= SRC1[3:0];
                        else if (ld_mcr) MCR <= SRC1[3:0];
 
 
        always @(posedge BCLK) ivarreg <= op_ok & (WRADR[5:1] == 5'd7) & WREN;  // IVAR0/1 = Reg. Nr. 14/15
        assign IVAR_MUX = op_ok & (WRADR[5:1] == 5'd7) & WREN;  // IVAR0/1 = Reg. Nr. 14/15
 
        always @(posedge BCLK) ivarreg <= IVAR_MUX;
        assign IVAR = {ivarreg,PTB_SEL};
        assign IVAR = {ivarreg,PTB_SEL};
 
 
        always @(posedge BCLK) PTB_WR  <= op_ok & (WRADR[5:1] == 5'd6) & WREN;  // PTB0/1 = Reg. Nr. 12/13
        always @(posedge BCLK) PTB_WR  <= op_ok & (WRADR[5:1] == 5'd6) & WREN;  // PTB0/1 = Reg. Nr. 12/13
        always @(posedge BCLK) PTB_SEL <= WRADR[0];
        always @(posedge BCLK) PTB_SEL <= WRADR[0];
 
 

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