| Line 36... |
Line 36... |
// 1. ADDSUB Adder and Subtractor for 36 bit
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// 1. ADDSUB Adder and Subtractor for 36 bit
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// 2. SFPU_ADDSUB Single Precision Floating Point Adder/Subtractor and Converter
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// 2. SFPU_ADDSUB Single Precision Floating Point Adder/Subtractor and Converter
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// 3. SFPU_MUL Single Precision Floating Point Multiplier
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// 3. SFPU_MUL Single Precision Floating Point Multiplier
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 1. ADDSUB Adder and Subtractor for 36 bit
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// 1. ADDSUB Adder and Subtractor for 36 bit
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ADDSUB (dataa, datab, add_sub, result);
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module ADDSUB (dataa, datab, add_sub, result);
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input [35:0] dataa,datab;
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input [35:0] dataa,datab;
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input add_sub; // 1 = Addition , 0 = Subtraction
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input add_sub; // 1 = Addition , 0 = Subtraction
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output [35:0] result;
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output [35:0] result;
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assign result = dataa + (add_sub ? datab : ~datab) + {35'd0,~add_sub};
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assign result = dataa + (add_sub ? datab : ~datab) + {35'd0,~add_sub};
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endmodule
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endmodule
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. SFPU_ADDSUB Single Precision Floating Point Adder/Subtractor and Converter
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// 2. SFPU_ADDSUB Single Precision Floating Point Adder/Subtractor and Converter
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SFPU_ADDSUB ( SRC1, SRC2, NZEXP, BWD, SELECT, OUT, IOUT, CMPRES );
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module SFPU_ADDSUB ( SRC1, SRC2, NZEXP, BWD, SELECT, OUT, IOUT, CMPRES );
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input [31:0] SRC1,SRC2; // Input data
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input [31:0] SRC1,SRC2; // Input data
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input [2:1] NZEXP;
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input [2:1] NZEXP;
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input [1:0] BWD; // size of integer
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input [1:0] BWD; // size of integer
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| Line 128... |
Line 128... |
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assign exdiff = {1'b0,SRC2[30:23]} - {1'b0,SRC1[30:23]}; // Difference of Exponents
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assign exdiff = {1'b0,SRC2[30:23]} - {1'b0,SRC1[30:23]}; // Difference of Exponents
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assign madiff = {1'b0,SRC2[22:0]} - {1'b0,SRC1[22:0]}; // Difference of Mantissas
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assign madiff = {1'b0,SRC2[22:0]} - {1'b0,SRC1[22:0]}; // Difference of Mantissas
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// if exdiff = 0 the shifter to the right is not needed !
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// if exdiff = 0 the shifter to the right is not needed !
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assign variante = (exdiff[8:1] == 8'h00) | (exdiff == 9'h1FF) | SELECT[1]; // MUX at the end, ROUND
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assign variante = (exdiff[8:1] == 8'h00) | (exdiff == 9'h1FF) | SELECT[1]; // MUX at the end, ROUND/TRUNC/MOViF uses case 1
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// ++++++++++++++++++++++++++ 1. case works on MOViF +++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++ 1. case works on MOViF +++++++++++++++++++++++++++++++++++++++
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assign switch = exdiff[8] | ((exdiff[7:0] == 8'h0) & madiff[23]); // exchange ?
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assign switch = exdiff[8] | ((exdiff[7:0] == 8'h0) & madiff[23]); // exchange ?
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| Line 167... |
Line 167... |
assign vorz = switch ? (SELECT[0] ^ sign1) : sign2;
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assign vorz = switch ? (SELECT[0] ^ sign1) : sign2;
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assign addflag = ~(SELECT[0] ^ (sign1 ^ sign2));
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assign addflag = ~(SELECT[0] ^ (sign1 ^ sign2));
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// CMPF : 1. step : what happend if Invalid Operand occurs - no Flag update !
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// CMPF : 1. step : what happend if Invalid Operand occurs - no Flag update !
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assign CMPRES[1] = ~CMPRES[0] & (switch ? ~sign1 : sign2); // see table above : N-Bit=1 if SRC1 >
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assign CMPRES[1] = ~CMPRES[0] & (switch ? ~sign1 : sign2); // see table above : N-Bit=1 if SRC1 > SRC2
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assign CMPRES[0] = (SRC1 == SRC2) | (~NZEXP[2] & ~NZEXP[1]); // Z-Bit : SRC1=SRC2, +0.0 = -0.0
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assign CMPRES[0] = (SRC1 == SRC2) | (~NZEXP[2] & ~NZEXP[1]); // Z-Bit : SRC1=SRC2, +0.0 = -0.0
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// ++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++
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// ADD/SUB : 3. step : prepare of Barrelshifter Left
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// ADD/SUB : 3. step : prepare of Barrelshifter Left
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| Line 232... |
Line 232... |
wire [8:0] exdiff12;
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wire [8:0] exdiff12;
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wire [23:0] muxsrc1;
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wire [23:0] muxsrc1;
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wire [32:9] pipe1; // numbering special for Right Shifter
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wire [32:9] pipe1; // numbering special for Right Shifter
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wire [4:0] shift;
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wire [4:0] shift;
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// the difference between SRC1 and SRC2 is bigger/equal 4:1 => no Barrelshifter after ADDSUB neccess
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// the difference between SRC1 and SRC2 is bigger/equal 4:1 => no Barrelshifter after ADDSUB neccessary
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assign vswitch = exdiff[8]; // exchange ?
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assign vswitch = exdiff[8]; // exchange ?
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assign shift1 = (exdiff[7:5] != 3'h0) ? 5'h1F : exdiff[4:0];
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assign shift1 = (exdiff[7:5] != 3'h0) ? 5'h1F : exdiff[4:0];
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assign exdiff12 = {1'b0,SRC1[30:23]} - {1'b0,SRC2[30:23]}; // caclulate already
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assign exdiff12 = {1'b0,SRC1[30:23]} - {1'b0,SRC2[30:23]}; // caclulate already
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assign shift2 = (exdiff12[7:5] != 3'h0) ? 5'h1F : exdiff12[4:0];
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assign shift2 = (exdiff12[7:5] != 3'h0) ? 5'h1F : exdiff12[4:0];
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assign muxsrc2 = vswitch ? {SRC1[30:23],1'b1,SRC1[22:0]} : {SRC2[30:23],1'b1,SRC2[22:0]}; // Includ
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assign muxsrc2 = vswitch ? {SRC1[30:23],1'b1,SRC1[22:0]} : {SRC2[30:23],1'b1,SRC2[22:0]}; // Including exponent
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assign muxsrc1 = vswitch ? {NZEXP[2],SRC2[22:0]} : {NZEXP[1],SRC1[22:0]};
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assign muxsrc1 = vswitch ? {NZEXP[2],SRC2[22:0]} : {NZEXP[1],SRC1[22:0]};
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assign pipe1 = SELECT[1] ? (ganzklein ? 24'h0 : {NZEXP[1],SRC1[22:0]}) : muxsrc1; // Feeding in R.T
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assign pipe1 = SELECT[1] ? (ganzklein ? 24'h0 : {NZEXP[1],SRC1[22:0]}) : muxsrc1; // Feeding in R.T.F.
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assign shift = SELECT[1] ? rexdiff[4:0] : (vswitch ? shift2 : shift1);
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assign shift = SELECT[1] ? rexdiff[4:0] : (vswitch ? shift2 : shift1);
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// ++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++
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// ADD/SUB + ROUND/TRUNC/FLOOR : 2. step : Barrelshifter to right -->
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// ADD/SUB + ROUND/TRUNC/FLOOR : 2. step : Barrelshifter to right -->
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| Line 275... |
Line 275... |
assign inex = brshifte[1:0]; // Inexact-Flag-Data via multiplexer at the end
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assign inex = brshifte[1:0]; // Inexact-Flag-Data via multiplexer at the end
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always @(SELECT or sign1 or brshifte or inex or ganzklein)
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always @(SELECT or sign1 or brshifte or inex or ganzklein)
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casex (SELECT[3:2])
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casex (SELECT[3:2])
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2'b00 : car_ry = sign1 ^ ((brshifte[2:0] == 3'b110) | (inex == 2'b11)); // ROUNDLi
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2'b00 : car_ry = sign1 ^ ((brshifte[2:0] == 3'b110) | (inex == 2'b11)); // ROUNDLi
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2'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2'b00)) : 1'b0; // +numbers like TRUNCLi, -num
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2'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2'b00)) : 1'b0; // +numbers like TRUNCLi, -numbers round to "-infinity"
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default : car_ry = sign1; // TRUNCLi , simple cut
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default : car_ry = sign1; // TRUNCLi , simple cut
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endcase
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endcase
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assign compl = sign1 ? ~brshifte[32:2] : brshifte[32:2];
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assign compl = sign1 ? ~brshifte[32:2] : brshifte[32:2];
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| Line 311... |
Line 311... |
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ADDSUB addsub_v (.dataa({1'b0,muxsrc2,3'b000}),
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ADDSUB addsub_v (.dataa({1'b0,muxsrc2,3'b000}),
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.datab({9'h0,brshifte[32:7],lsb}), .add_sub(addflag),
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.datab({9'h0,brshifte[32:7],lsb}), .add_sub(addflag),
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.result(vresult) );
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.result(vresult) );
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assign eminus1 = muxsrc2[31:24] - 8'h01; // a greater Underflow can not exist, because minimal Expo
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assign eminus1 = muxsrc2[31:24] - 8'h01; // a greater Underflow can not exist, because minimal Exponent = 0..01
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// Case ADD : Bit 23 : LSB of exponent
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// Case ADD : Bit 23 : LSB of exponent
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assign vadd_q = (muxsrc2[24] != vresult[27]) ? {vresult[35:3],(vresult[2:0] != 3'b000)}
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assign vadd_q = (muxsrc2[24] != vresult[27]) ? {vresult[35:3],(vresult[2:0] != 3'b000)}
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: {vresult[35:27],vresult[25:2],(vresult[1:0] != 2'b00)} ;
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: {vresult[35:27],vresult[25:2],(vresult[1:0] != 2'b00)} ;
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// Case SUB : Bit 26 : "hidden" MSB of mantissa
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// Case SUB : Bit 26 : "hidden" MSB of mantissa
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assign vsub_q = vresult[26] ? {vresult[35:27], vresult[25:2],(vresult[1:0] != 2'b00)} // like t
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assign vsub_q = vresult[26] ? {vresult[35:27], vresult[25:2],(vresult[1:0] != 2'b00)} // like the vadd_q "0" case
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: {vresult[35],eminus1,vresult[24:0]} ;
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: {vresult[35],eminus1,vresult[24:0]} ;
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// SELECT[1] has here no meaning
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// SELECT[1] has here no meaning
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assign vzero = (vresult[26:0] == 27'h0) & ~addflag; // only if "-" can be the result 0
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assign vzero = (vresult[26:0] == 27'h0) & ~addflag; // only if "-" can be the result 0
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| Line 331... |
Line 331... |
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assign OUT = variante ? out_v1 : out_v0; // Last multiplexer
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assign OUT = variante ? out_v1 : out_v0; // Last multiplexer
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endmodule
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endmodule
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 3. SFPU_MUL Single Precision Floating Point Multiplier
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// 3. SFPU_MUL Single Precision Floating Point Multiplier
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SFPU_MUL ( SRC1, SRC2, MRESULT, NZEXP, OUT);
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module SFPU_MUL ( SRC1, SRC2, MRESULT, NZEXP, OUT);
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input [31:0] SRC1,SRC2; // only exponent of input data used
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input [31:0] SRC1,SRC2; // only exponent of input data used
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input [47:0] MRESULT;
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input [47:0] MRESULT;
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input [2:1] NZEXP; // Flags of input data
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input [2:1] NZEXP; // Flags of input data
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| Line 364... |
Line 364... |
assign OUT = MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}
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assign OUT = MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}
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: {zero,sign,expol,MRESULT[45:23],restlow};
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: {zero,sign,expol,MRESULT[45:23],restlow};
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endmodule
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endmodule
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SP_FPU (BCLK, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX
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module SP_FPU (BCLK, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
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input BCLK; // is not used !
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input BCLK; // is not used !
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input [7:0] OPCODE;
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input [7:0] OPCODE;
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input [31:0] SRC1,SRC2; // Input data
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input [31:0] SRC1,SRC2; // Input data
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input [8:3] FSR; // Floating Point Status Register
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input [8:3] FSR; // Floating Point Status Register
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| Line 412... |
Line 412... |
default : select = 4'b0;
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default : select = 4'b0;
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endcase
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endcase
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assign SP_MUX = select[3] & (select[1:0] != 2'b11) & FL; // Output multiplexer
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assign SP_MUX = select[3] & (select[1:0] != 2'b11) & FL; // Output multiplexer
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assign LD_FSR = (OPCODE[7:4] == 4'h9) & (OPCODE[3:1] == 3'b001); // LFSR does only Double (accordin
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assign LD_FSR = (OPCODE[7:4] == 4'h9) & (OPCODE[3:1] == 3'b001); // LFSR does only Double (according datasheet NS32016)
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assign UP_SP = select[3] & FL; // All FPU opcodes of SP_FPU
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assign UP_SP = select[3] & FL; // All FPU opcodes of SP_FPU
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assign op_cmp = (OPCODE == 8'hB2) & FL;
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assign op_cmp = (OPCODE == 8'hB2) & FL;
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// SRCFLAGS
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// SRCFLAGS
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