| Line 2... |
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: SP_FPU.v
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// Filename: SP_FPU.v
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// Version: 1.0
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// Version: 2.0
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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| Line 30... |
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Testversion mit Pipeline Register in SFPU_ADDSUB **************
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. ADDSUB Adder and Subtractor for 36 bit
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// 1. ADDSUB Adder and Subtractor for 36 bit
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// 2. SFPU_ADDSUB Single Precision Floating Point Adder/Subtractor and Converter
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// 2. SFPU_ADDSUB Single Precision Floating Point Adder/Subtractor and Converter
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// 3. SFPU_MUL Single Precision Floating Point Multiplier
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// 3. SFPU_MUL Single Precision Floating Point Multiplier
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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| Line 58... |
Line 61... |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. SFPU_ADDSUB Single Precision Floating Point Adder/Subtractor and Converter
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// 2. SFPU_ADDSUB Single Precision Floating Point Adder/Subtractor and Converter
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SFPU_ADDSUB ( SRC1, SRC2, NZEXP, BWD, SELECT, OUT, IOUT, CMPRES );
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module SFPU_ADDSUB ( BCLK, SRC1, SRC2, NZEXP, BWD, SELECT, OUT, IOUT, CMPRES );
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input BCLK;
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input [31:0] SRC1,SRC2; // Input data
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input [31:0] SRC1,SRC2; // Input data
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input [2:1] NZEXP;
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input [2:1] NZEXP;
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input [1:0] BWD; // size of integer
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input [1:0] BWD; // size of integer
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input [3:0] SELECT;
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input [3:0] SELECT;
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output [36:0] OUT; // the result
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output [36:0] OUT; // the result
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output [31:0] IOUT; // result of ROUNDFi/TRUNCFi/FLOORFi
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output reg [31:0] IOUT; // result of ROUNDFi/TRUNCFi/FLOORFi
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output [1:0] CMPRES;
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output reg [1:0] CMPRES;
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// ++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++
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// MOViF : 1. step
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// MOViF : 1. step
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reg [31:8] movdat;
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reg [31:0] movdat;
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wire [31:0] movif;
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wire [31:0] movif;
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always @(BWD or SRC1)
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always @(BWD or SRC1)
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casex({BWD,SRC1[15],SRC1[7]})
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casex(BWD)
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4'b00x0 : movdat = 24'h0000_00; // Byte
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2'b00 : movdat = {{24{SRC1[7]}}, SRC1[7:0]}; // Byte
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4'b00x1 : movdat = 24'hFFFF_FF;
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2'b01 : movdat = {{16{SRC1[15]}},SRC1[15:0]}; // Word
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4'b010x : movdat = {16'h0000,SRC1[15:8]}; // Word
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default : movdat = SRC1[31:0]; // Double
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4'b011x : movdat = {16'hFFFF,SRC1[15:8]};
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default : movdat = SRC1[31:8]; // Double
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endcase
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endcase
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assign movif = movdat[31] ? (32'h0 - {movdat,SRC1[7:0]}) : {movdat,SRC1[7:0]};
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assign movif = ({32{movdat[31]}} ^ movdat) + {31'h0,movdat[31]};
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// -2^31 is kept
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// -2^31 is kept
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// ROUNDFi/TRUNCFi/FLOORFi : 1. step
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// ROUNDFi/TRUNCFi/FLOORFi : 1. step
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reg ovflag,ovflag2;
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reg ovflag,ovflag2;
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wire [8:0] rexdiff,rexo;
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wire [8:0] rexdiff,rexo;
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wire rovfl,minint;
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reg rovfl;
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wire minint;
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wire ganzklein; // Flag for 0
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wire ganzklein; // Flag for 0
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assign rexdiff = 9'h09D - {1'b0,SRC1[30:23]}; // 4..0 is the right shift value
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assign rexdiff = 9'h09D - {1'b0,SRC1[30:23]}; // 4..0 is the right shift value
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assign rovfl = (ovflag | ovflag2) & (SELECT[1:0] == 2'b11) & ~minint;
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always @(posedge BCLK) rovfl <= (ovflag | ovflag2) & (SELECT[1:0] == 2'b11) & ~minint;
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assign ganzklein = (~rexdiff[8] & (rexdiff[7:5] != 3'b000)); // 0 is implicit via SRC1[30:23]=0
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assign ganzklein = (~rexdiff[8] & (rexdiff[7:5] != 3'b000)); // 0 is implicit via SRC1[30:23]=0
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// Detection of Overflow
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// Detection of Overflow
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assign rexo = ({1'b0,SRC1[30:23]} - {8'h3F,~BWD[1]}); // subtract B/W = 7F , D = 7E
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assign rexo = ({1'b0,SRC1[30:23]} - {8'h3F,~BWD[1]}); // subtract B/W = 7F , D = 7E
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Line 119... |
// ADD/SUB : 1. step : which operand ist bigger ? if required exchange
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// ADD/SUB : 1. step : which operand ist bigger ? if required exchange
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// SUB/CMP : SRC2 - SRC1
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// SUB/CMP : SRC2 - SRC1
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wire [8:0] exdiff;
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wire [8:0] exdiff;
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wire [23:0] madiff;
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wire [23:0] madiff;
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wire switch,sign,sign1,sign2;
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wire switch,sign1,sign2;
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wire variante;
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reg variante;
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wire vorz,addflag;
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wire vorz,addflag;
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wire [35:0] result_sw,result_nosw;
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wire [35:0] result,result_sw,result_nosw;
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wire [24:0] value1,value2;
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wire [24:0] value1,value2;
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wire cmp_res;
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wire [35:0] result;
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assign exdiff = {1'b0,SRC2[30:23]} - {1'b0,SRC1[30:23]}; // Difference of Exponents
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assign exdiff = {1'b0,SRC2[30:23]} - {1'b0,SRC1[30:23]}; // Difference of Exponents
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assign madiff = {1'b0,SRC2[22:0]} - {1'b0,SRC1[22:0]}; // Difference of Mantissas
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assign madiff = {1'b0,SRC2[22:0]} - {1'b0,SRC1[22:0]}; // Difference of Mantissas
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// if exdiff = 0 the shifter to the right is not needed !
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// if exdiff = 0 the shifter to the right is not needed ! MUX at the end, ROUND/TRUNC/MOViF uses case 1
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assign variante = (exdiff[8:1] == 8'h00) | (exdiff == 9'h1FF) | SELECT[1]; // MUX at the end, ROUND/TRUNC/MOViF uses case 1
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always @(posedge BCLK) variante <= (exdiff[8:1] == 8'h00) | (exdiff == 9'h1FF) | SELECT[1];
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// ++++++++++++++++++++++++++ 1. case works on MOViF +++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++ 1. case works on MOViF +++++++++++++++++++++++++++++++++++++++
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assign switch = exdiff[8] | ((exdiff[7:0] == 8'h0) & madiff[23]); // exchange ?
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assign switch = exdiff[8] | ((exdiff[7:0] == 8'h0) & madiff[23]); // exchange ?
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| Line 167... |
Line 169... |
assign vorz = switch ? (SELECT[0] ^ sign1) : sign2;
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assign vorz = switch ? (SELECT[0] ^ sign1) : sign2;
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assign addflag = ~(SELECT[0] ^ (sign1 ^ sign2));
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assign addflag = ~(SELECT[0] ^ (sign1 ^ sign2));
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// CMPF : 1. step : what happend if Invalid Operand occurs - no Flag update !
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// CMPF : 1. step : what happend if Invalid Operand occurs - no Flag update !
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assign CMPRES[1] = ~CMPRES[0] & (switch ? ~sign1 : sign2); // see table above : N-Bit=1 if SRC1 > SRC2
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assign cmp_res = (SRC1 == SRC2) | (~NZEXP[2] & ~NZEXP[1]); // Z-Bit : SRC1=SRC2, +0.0 = -0.0
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assign CMPRES[0] = (SRC1 == SRC2) | (~NZEXP[2] & ~NZEXP[1]); // Z-Bit : SRC1=SRC2, +0.0 = -0.0
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always @(posedge BCLK) CMPRES <= {(~cmp_res & (switch ? ~sign1 : sign2)),cmp_res}; // see table above : N-Bit=1 if SRC1 > SRC2
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// ++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++
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// ADD/SUB : 3. step : prepare of Barrelshifter Left
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// ADD/SUB : 3. step : prepare of Barrelshifter Left
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wire [31:0] blshift;
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wire [31:0] blshift;
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wire [9:0] shiftl;
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reg [9:0] shiftl;
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wire shift_16;
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wire shift_16;
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wire [33:0] add_q;
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reg [33:0] add_q;
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wire [31:0] muxsrc2;
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wire [31:0] muxsrc2;
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wire [1:0] inex;
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wire [1:0] inex;
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assign blshift = SELECT[1] ? movif : {result[26:0],5'h00}; // Feeding of MOViF
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assign blshift = SELECT[1] ? movif : {result[26:0],5'h00}; // Feeding of MOViF
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assign shiftl = SELECT[1] ? 10'h09E : {1'b0,result[35:27]}; // MOViF
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always @(posedge BCLK) shiftl <= SELECT[1] ? 10'h09E : {1'b0,result[35:27]}; // MOViF
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assign shift_16 = (blshift[31:16] == 16'h0000);
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assign shift_16 = (blshift[31:16] == 16'h0000);
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// In case of ADD the result bypasses the Barrelshifter left
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// In case of ADD the result bypasses the Barrelshifter left
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assign add_q = (muxsrc2[24] != result[27]) ? {result[35:3],(result[2:0] != 3'b000)}
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always @(posedge BCLK) add_q <= (muxsrc2[24] != result[27]) ? {result[35:3],(result[2:0] != 3'b000)}
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: {result[35:27],result[25:2],(result[1:0] != 2'b00)} ;
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: {result[35:27],result[25:2],(result[1:0] != 2'b00)} ;
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// ++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++
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// ADD/SUB : 4. step : Barrelshifter left for SUB and MOViF :
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// ADD/SUB : 4. step : Barrelshifter left for SUB and MOViF :
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wire shift_8,shift_4,shift_2,shift_1,zero;
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wire shift_8,shift_4,shift_2,shift_1;
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wire [1:0] lsb_bl;
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wire [1:0] lsb_bl;
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wire [31:0] blshifta,blshiftb,blshiftc,blshiftd,blshifte;
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wire [31:0] blshifta,blshiftc,blshiftd,blshifte;
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reg [31:0] blshiftb;
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wire [9:0] expol;
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wire [9:0] expol;
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wire [36:0] out_v1;
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wire [36:0] out_v1;
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reg [1:0] rinex;
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reg zero,sign,select_v1;
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reg [4:3] pshift;
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assign blshifta = shift_16 ? {blshift[15:0],16'h0000} : blshift;
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assign blshifta = shift_16 ? {blshift[15:0],16'd0} : blshift;
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assign shift_8 = (blshifta[31:24] == 8'h00);
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assign shift_8 = (blshifta[31:24] == 8'h00);
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assign blshiftb = shift_8 ? {blshifta[23:0],8'h00} : blshifta;
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always @(posedge BCLK)
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blshiftb <= shift_8 ? {blshifta[23:0],8'd0} : blshifta;
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assign shift_4 = (blshiftb[31:28] == 4'h0);
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assign shift_4 = (blshiftb[31:28] == 4'h0);
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assign blshiftc = shift_4 ? {blshiftb[27:0],4'h0} : blshiftb;
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assign blshiftc = shift_4 ? {blshiftb[27:0],4'd0} : blshiftb;
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assign shift_2 = (blshiftc[31:30] == 2'b00);
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assign shift_2 = (blshiftc[31:30] == 2'b00);
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assign blshiftd = shift_2 ? {blshiftc[29:0],2'b00} : blshiftc;
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assign blshiftd = shift_2 ? {blshiftc[29:0],2'd0} : blshiftc;
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assign shift_1 = ~blshiftd[31];
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assign shift_1 = ~blshiftd[31];
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assign blshifte = shift_1 ? {blshiftd[30:0],1'b0} : blshiftd;
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assign blshifte = shift_1 ? {blshiftd[30:0],1'b0} : blshiftd;
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always @(posedge BCLK) pshift <= {shift_16,shift_8};
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// Overflow at ROUNDFi/TRUNCFi/FLOORFi via overflow in exponent shown, SELECT[1] is then 1 !
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// Overflow at ROUNDFi/TRUNCFi/FLOORFi via overflow in exponent shown, SELECT[1] is then 1 !
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assign expol = (shiftl - {5'h00,shift_16,shift_8,shift_4,shift_2,shift_1}) | {1'b0,rovfl,8'h00};
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assign expol = (shiftl - {5'h00,pshift,shift_4,shift_2,shift_1}) | {1'b0,rovfl,8'd0};
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always @(posedge BCLK) rinex <= inex;
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// Inexact at ROUNDFi/TRUNCFi/FLOORFi : evaluation for all one level higher
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// Inexact at ROUNDFi/TRUNCFi/FLOORFi : evaluation for all one level higher
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assign lsb_bl = (SELECT[1:0] == 2'b11) ? inex : {blshifte[7],(blshifte[6:0] != 7'h00)};
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assign lsb_bl = (SELECT[1:0] == 2'b11) ? rinex : {blshifte[7],(blshifte[6:0] != 7'd0)};
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assign zero = (~SELECT[1] & ~NZEXP[2] & ~NZEXP[1])
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always @(posedge BCLK) zero <= (~SELECT[1] & ~NZEXP[2] & ~NZEXP[1])
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| ((blshift == 32'h0) & ((~addflag & ~SELECT[1]) | (SELECT[1:0] == 2'b10)));
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| ((blshift == 32'h0) & ((~addflag & ~SELECT[1]) | (SELECT[1:0] == 2'b10)));
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assign sign = SELECT[1] ? movdat[31] : vorz;
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always @(posedge BCLK) sign <= SELECT[1] ? movdat[31] : vorz;
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always @(posedge BCLK) select_v1 <= addflag & ~SELECT[1];
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assign out_v1 = (addflag & ~SELECT[1]) ? {zero,sign,1'b0,add_q}
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assign out_v1 = select_v1 ? {zero,sign,1'b0,add_q}
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: {zero,sign,expol,blshifte[30:8],lsb_bl};
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: {zero,sign,expol,blshifte[30:8],lsb_bl};
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// +++++++++++++++++++++++++ 2. case works on ROUND/TRUNC/FLOOR ++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++ 2. case works on ROUND/TRUNC/FLOOR ++++++++++++++++++++++++++++++++++
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wire vswitch;
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wire vswitch;
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| Line 267... |
Line 279... |
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// ++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++
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// ROUNDFi/TRUNCFi/FLOORFi : 3. step : round to integer
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// ROUNDFi/TRUNCFi/FLOORFi : 3. step : round to integer
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reg car_ry;
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reg car_ry;
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wire [30:0] compl;
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wire [32:0] iadder;
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wire [31:0] iadder;
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assign inex = brshifte[1:0]; // Inexact-Flag-Data via multiplexer at the end
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assign inex = brshifte[1:0]; // Inexact-Flag-Data via multiplexer at the end
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always @(SELECT or sign1 or brshifte or inex or ganzklein)
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always @(SELECT or sign1 or brshifte or inex or ganzklein)
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casex (SELECT[3:2])
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casex (SELECT[3:2])
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2'b00 : car_ry = sign1 ^ ((brshifte[2:0] == 3'b110) | (inex == 2'b11)); // ROUNDLi
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2'b00 : car_ry = sign1 ^ ((brshifte[2:0] == 3'b110) | (inex == 2'b11)); // ROUNDLi
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2'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2'b00)) : 1'b0; // +numbers like TRUNCLi, -numbers round to "-infinity"
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2'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2'b00)) : 1'b0; // +numbers like TRUNCLi, -numbers round to "-infinity"
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default : car_ry = sign1; // TRUNCLi , simple cut
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default : car_ry = sign1; // TRUNCLi , simple cut
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endcase
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endcase
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assign compl = sign1 ? ~brshifte[32:2] : brshifte[32:2];
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assign iadder = (sign1 ? {2'b11,~brshifte[32:2]} : {2'b0,brshifte[32:2]}) + {32'h0,car_ry};
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assign iadder = {sign1,compl} + {31'h0,car_ry};
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assign IOUT = minint ? 32'h8000_0000 : iadder;
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always @(posedge BCLK) IOUT <= minint ? 32'h8000_0000 : iadder[31:0];
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always @(iadder or BWD or sign1) // special overflow detection i.e. -129 bis -255 bei Byte
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always @(iadder or BWD or sign1) // special overflow detection i.e. -129 bis -255 bei Byte
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casex (BWD) // or 127.9 -> 128 = Fehler !
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casex (BWD) // or 127.9 -> 128 = Fehler !
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2'b00 : ovflag2 = (iadder[8] != iadder[7]); // Byte
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2'b00 : ovflag2 = (iadder[8] != iadder[7]); // Byte
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2'b01 : ovflag2 = (iadder[16] != iadder[15]); // Word
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2'b01 : ovflag2 = (iadder[16] != iadder[15]); // Word
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default : ovflag2 = 1'b0;
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default : ovflag2 = (iadder[32] != iadder[31]); // Double
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endcase
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endcase
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// ++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++
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// only ADD/SUB : 3. step : Add or Subtract
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// only ADD/SUB : 3. step : Add or Subtract
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// the modul ADDSUB integrates the carry from the mantissa : 35 Bit
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// the modul ADDSUB integrates the carry from the mantissa : 35 Bit
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| Line 301... |
Line 310... |
wire lsb;
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wire lsb;
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wire [35:0] vresult;
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wire [35:0] vresult;
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wire [7:0] eminus1;
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wire [7:0] eminus1;
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wire [33:0] vadd_q,vsub_q;
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wire [33:0] vadd_q,vsub_q;
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wire vzero;
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wire vzero;
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wire [36:0] out_v0;
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reg [36:0] out_v0;
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|
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assign lsb = (brshifte[6:0] != 7'h00);
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assign lsb = (brshifte[6:0] != 7'h00);
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|
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// Adder-Definition : "0"(8 Bit Exponent)"1"(23 Bit Mantissa)"000"
|
// Adder-Definition : "0"(8 Bit Exponent)"1"(23 Bit Mantissa)"000"
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| Line 322... |
Line 331... |
// Case SUB : Bit 26 : "hidden" MSB of mantissa
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// Case SUB : Bit 26 : "hidden" MSB of mantissa
|
assign vsub_q = vresult[26] ? {vresult[35:27], vresult[25:2],(vresult[1:0] != 2'b00)} // like the vadd_q "0" case
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assign vsub_q = vresult[26] ? {vresult[35:27], vresult[25:2],(vresult[1:0] != 2'b00)} // like the vadd_q "0" case
|
: {vresult[35],eminus1,vresult[24:0]} ;
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: {vresult[35],eminus1,vresult[24:0]} ;
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|
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// SELECT[1] has here no meaning
|
// SELECT[1] has here no meaning
|
assign vzero = (vresult[26:0] == 27'h0) & ~addflag; // only if "-" can be the result 0
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assign vzero = (vresult[26:0] == 27'h0); // only if "-" can be the result 0
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|
|
assign out_v0 = addflag ? {vzero,vorz,1'b0,vadd_q}
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always @(posedge BCLK) out_v0 <= addflag ? { 1'b0,vorz,1'b0,vadd_q}
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: {vzero,vorz,1'b0,vsub_q} ;
|
: {vzero,vorz,1'b0,vsub_q} ;
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|
|
assign OUT = variante ? out_v1 : out_v0; // Last multiplexer
|
assign OUT = variante ? out_v1 : out_v0; // Last multiplexer
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|
|
endmodule
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endmodule
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| Line 336... |
Line 345... |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 3. SFPU_MUL Single Precision Floating Point Multiplier
|
// 3. SFPU_MUL Single Precision Floating Point Multiplier
|
//
|
//
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SFPU_MUL ( SRC1, SRC2, MRESULT, NZEXP, OUT);
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module SFPU_MUL ( BCLK, SRC1, SRC2, MRESULT, NZEXP, OUT);
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input BCLK;
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input [31:0] SRC1,SRC2; // only exponent of input data used
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input [31:0] SRC1,SRC2; // only exponent of input data used
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input [47:0] MRESULT;
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input [47:0] MRESULT;
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input [2:1] NZEXP; // Flags of input data
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input [2:1] NZEXP; // Flags of input data
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output [36:0] OUT; // The result
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output reg [36:0] OUT; // The result
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wire [9:0] exponent,expoh,expol;
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wire [9:0] exponent,expoh,expol;
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wire [1:0] restlow,resthigh;
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wire [1:0] restlow,resthigh;
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wire zero,sign,orlow;
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wire zero,sign,orlow;
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| Line 359... |
Line 369... |
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assign exponent = {2'b00,SRC1[30:23]} + {2'b00,SRC2[30:23]};
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assign exponent = {2'b00,SRC1[30:23]} + {2'b00,SRC2[30:23]};
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assign expoh = exponent - 10'h07E;
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assign expoh = exponent - 10'h07E;
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assign expol = exponent - 10'h07F; // for MSB if MRESULT=0
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assign expol = exponent - 10'h07F; // for MSB if MRESULT=0
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assign OUT = MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}
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always @(posedge BCLK) OUT <= MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}
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: {zero,sign,expol,MRESULT[45:23],restlow};
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: {zero,sign,expol,MRESULT[45:23],restlow};
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SP_FPU (BCLK, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
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module SP_FPU (BCLK, START, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
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input BCLK; // is not used !
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input BCLK; // is not used !
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input START;
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input [7:0] OPCODE;
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input [7:0] OPCODE;
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input [31:0] SRC1,SRC2; // Input data
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input [31:0] SRC1,SRC2; // Input data
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input [8:3] FSR; // Floating Point Status Register
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input [8:3] FSR; // Floating Point Status Register
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input [47:0] MRESULT; // Multiplier result
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input [47:0] MRESULT; // Multiplier result
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input [1:0] BWD; // Size of integer
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input [1:0] BWD; // Size of integer
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input FL;
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input FL;
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output [31:0] FP_OUT,I_OUT; // The results
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output [31:0] FP_OUT,I_OUT; // The results
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output [4:0] TT_SP; // Trap-Type
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output [4:0] TT_SP; // Trap-Type
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output [2:0] SP_CMP; // CMPF result
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output [2:0] SP_CMP; // CMPF result
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output SP_MUX,LD_FSR,UP_SP;
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output SP_MUX,LD_FSR;
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output reg UP_SP;
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reg [2:0] tt;
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reg [2:0] tt;
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reg [3:0] select;
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reg [3:0] select;
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reg nan;
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reg car_ry;
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reg car_ry;
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wire [36:0] mulout,addout,fpout;
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wire [36:0] mulout,addout,fpout;
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wire [2:1] nzexp;
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wire [2:1] nzexp;
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wire [34:2] rund; // Indexnumbers like xxxout
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wire [34:2] rund; // Indexnumbers like xxxout
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wire overflow,underflow,inexact;
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wire overflow,underflow,inexact;
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wire op_cmp;
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wire op_cmp;
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wire nan,nan_1,nan_2;
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wire nan_1,nan_2;
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// Control of datapath
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// Control of datapath
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always @(OPCODE)
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always @(OPCODE)
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casex (OPCODE)
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casex (OPCODE)
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| Line 413... |
Line 426... |
endcase
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endcase
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assign SP_MUX = select[3] & (select[1:0] != 2'b11) & FL; // Output multiplexer
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assign SP_MUX = select[3] & (select[1:0] != 2'b11) & FL; // Output multiplexer
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assign LD_FSR = (OPCODE[7:4] == 4'h9) & (OPCODE[3:1] == 3'b001); // LFSR does only Double (according datasheet NS32016)
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assign LD_FSR = (OPCODE[7:4] == 4'h9) & (OPCODE[3:1] == 3'b001); // LFSR does only Double (according datasheet NS32016)
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assign UP_SP = select[3] & FL; // All FPU opcodes of SP_FPU
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always @(posedge BCLK) UP_SP = select[3] & FL & START; // All FPU opcodes of SP_FPU, all are using 2 Clock
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assign op_cmp = (OPCODE == 8'hB2) & FL;
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assign op_cmp = (OPCODE == 8'hB2) & FL;
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// SRCFLAGS
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// SRCFLAGS
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assign nzexp[2] = (SRC2[30:23] != 8'd0); // only exponent 0 ,denormalized Number => NAN !
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assign nzexp[2] = (SRC2[30:23] != 8'd0); // only exponent 0 ,denormalized Number => NAN !
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assign nzexp[1] = (SRC1[30:23] != 8'd0); // only exponent 0 ,denormalized Number => NAN !
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assign nzexp[1] = (SRC1[30:23] != 8'd0); // only exponent 0 ,denormalized Number => NAN !
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assign nan_2 = (SRC2[30:23] == 8'hFF) | (~nzexp[2] & (SRC2[22:0] != 23'd0)); // NAN
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assign nan_2 = (SRC2[30:23] == 8'hFF) | (~nzexp[2] & (SRC2[22:0] != 23'd0)); // NAN
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assign nan_1 = (SRC1[30:23] == 8'hFF) | (~nzexp[1] & (SRC1[22:0] != 23'd0)); // NAN
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assign nan_1 = (SRC1[30:23] == 8'hFF) | (~nzexp[1] & (SRC1[22:0] != 23'd0)); // NAN
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assign nan = (select[1:0] == 2'b11) ? nan_1 : (~select[1] & (nan_2 | nan_1));
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always @(posedge BCLK) nan <= (select[1:0] == 2'b11) ? nan_1 : (~select[1] & (nan_2 | nan_1));
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// 001 : ADDF,... + 011 : CMPF
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// 001 : ADDF,... + 011 : CMPF
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SFPU_ADDSUB IADDSUB ( .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .BWD(BWD),
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SFPU_ADDSUB IADDSUB ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .BWD(BWD),
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.SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );
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.SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );
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// 100 : MULF
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// 100 : MULF
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SFPU_MUL IMUL ( .SRC1(SRC1), .SRC2(SRC2), .MRESULT(MRESULT), .OUT(mulout), .NZEXP(nzexp) );
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SFPU_MUL IMUL ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .MRESULT(MRESULT), .OUT(mulout), .NZEXP(nzexp) );
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// FP - Pfad : selection of result and rounding :
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// FP - Pfad : selection of result and rounding :
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assign fpout = (OPCODE[5] & OPCODE[3]) ? mulout : addout;
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assign fpout = (OPCODE[5] & OPCODE[3]) ? mulout : addout;
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