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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: SP_FPU.v
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// Filename: SP_FPU.v
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// Version: 2.0
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// Version: 3.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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// Date: 2 December 2018
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Testversion mit Pipeline Register in SFPU_ADDSUB **************
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// Testversion mit Pipeline Register in SFPU_ADDSUB **************
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. ADDSUB Adder and Subtractor for 36 bit
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// 1. ADDSUB Adder and Subtractor for 36 bit
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 3. SFPU_MUL Single Precision Floating Point Multiplier
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// 3. SFPU_MUL Single Precision Floating Point Multiplier
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SFPU_MUL ( BCLK, SRC1, SRC2, MRESULT, NZEXP, OUT);
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module SFPU_MUL ( BCLK, SRC1, SRC2, NZEXP, OUT);
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input BCLK;
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input BCLK;
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input [31:0] SRC1,SRC2; // only exponent of input data used
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input [31:0] SRC1,SRC2; // only exponent of input data used
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input [47:0] MRESULT;
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input [2:1] NZEXP; // Flags of input data
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input [2:1] NZEXP; // Flags of input data
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output reg [36:0] OUT; // The result
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output reg [36:0] OUT; // The result
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wire [47:0] mresult;
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wire [9:0] exponent,expoh,expol;
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wire [9:0] exponent,expoh,expol;
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wire [1:0] restlow,resthigh;
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wire [1:0] restlow,resthigh;
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wire zero,sign,orlow;
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wire zero,sign,orlow;
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assign mresult = {1'b1,SRC1[22:0]} * {1'b1,SRC2[22:0]}; // Unsigned Multiplier
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assign zero = ~NZEXP[2] | ~NZEXP[1]; // one of both NULL -> NULL is the result
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assign zero = ~NZEXP[2] | ~NZEXP[1]; // one of both NULL -> NULL is the result
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assign sign = (SRC1[31] ^ SRC2[31]) & ~zero;
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assign sign = (SRC1[31] ^ SRC2[31]) & ~zero;
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assign orlow = (MRESULT[21:0] != 22'b0);
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assign orlow = (mresult[21:0] != 22'b0);
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assign restlow = {MRESULT[22],orlow};
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assign restlow = {mresult[22],orlow};
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assign resthigh = {MRESULT[23],(MRESULT[22] | orlow)};
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assign resthigh = {mresult[23],(mresult[22] | orlow)};
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assign exponent = {2'b00,SRC1[30:23]} + {2'b00,SRC2[30:23]};
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assign exponent = {2'b00,SRC1[30:23]} + {2'b00,SRC2[30:23]};
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assign expoh = exponent - 10'h07E;
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assign expoh = exponent - 10'h07E;
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assign expol = exponent - 10'h07F; // for MSB if MRESULT=0
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assign expol = exponent - 10'h07F; // for MSB if mresult=0
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always @(posedge BCLK) OUT <= MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}
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always @(posedge BCLK) OUT <= mresult[47] ? {zero,sign,expoh,mresult[46:24],resthigh}
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: {zero,sign,expol,MRESULT[45:23],restlow};
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: {zero,sign,expol,mresult[45:23],restlow};
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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// 4. SP_FPU Top Level of Single Precision Floating Point Unit
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module SP_FPU (BCLK, START, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
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module SP_FPU (BCLK, START, OPCODE, SRC1, SRC2, FSR, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
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input BCLK; // is not used !
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input BCLK; // is not used !
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input START;
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input START;
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input [7:0] OPCODE;
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input [7:0] OPCODE;
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input [31:0] SRC1,SRC2; // Input data
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input [31:0] SRC1,SRC2; // Input data
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input [8:3] FSR; // Floating Point Status Register
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input [8:3] FSR; // Floating Point Status Register
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input [47:0] MRESULT; // Multiplier result
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input [1:0] BWD; // Size of integer
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input [1:0] BWD; // Size of integer
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input FL;
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input FL;
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output [31:0] FP_OUT,I_OUT; // The results
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output [31:0] FP_OUT,I_OUT; // The results
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output [4:0] TT_SP; // Trap-Type
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output [4:0] TT_SP; // Trap-Type
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// 001 : ADDF,... + 011 : CMPF
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// 001 : ADDF,... + 011 : CMPF
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SFPU_ADDSUB IADDSUB ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .BWD(BWD),
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SFPU_ADDSUB IADDSUB ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .BWD(BWD),
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.SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );
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.SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );
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// 100 : MULF
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// 100 : MULF
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SFPU_MUL IMUL ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .MRESULT(MRESULT), .OUT(mulout), .NZEXP(nzexp) );
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SFPU_MUL IMUL ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .OUT(mulout) );
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// FP - Pfad : selection of result and rounding :
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// FP - Pfad : selection of result and rounding :
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assign fpout = (OPCODE[5] & OPCODE[3]) ? mulout : addout;
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assign fpout = (OPCODE[5] & OPCODE[3]) ? mulout : addout;
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