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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//
// This file is part of the M32632 project
// This file is part of the M32632 project
// http://opencores.org/project,m32632
// http://opencores.org/project,m32632
//
//
//      Filename:       SP_FPU.v
//      Filename:       SP_FPU.v
//      Version:        2.0
//      Version:        3.0
//      History:        1.0 first release of 30 Mai 2015
//      History:        1.0 first release of 30 Mai 2015
//      Date:           14 August 2016
//      Date:           2 December 2018
//
//
// Copyright (C) 2016 Udo Moeller
// Copyright (C) 2018 Udo Moeller
// 
// 
// This source file may be used and distributed without 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// restriction provided that this copyright statement is not 
// removed from the file and that any derivative work contains 
// removed from the file and that any derivative work contains 
// the original copyright notice and the associated disclaimer.
// the original copyright notice and the associated disclaimer.
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// 
// 
// You should have received a copy of the GNU Lesser General 
// You should have received a copy of the GNU Lesser General 
// Public License along with this source; if not, download it 
// Public License along with this source; if not, download it 
// from http://www.opencores.org/lgpl.shtml 
// from http://www.opencores.org/lgpl.shtml 
// 
// 
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//
//      Testversion mit Pipeline Register in SFPU_ADDSUB **************
//      Testversion mit Pipeline Register in SFPU_ADDSUB **************
//
//
//      Modules contained in this file:
//      Modules contained in this file:
//      1. ADDSUB               Adder and Subtractor for 36 bit
//      1. ADDSUB               Adder and Subtractor for 36 bit
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//
//      3. SFPU_MUL             Single Precision Floating Point Multiplier
//      3. SFPU_MUL             Single Precision Floating Point Multiplier
//
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module SFPU_MUL ( BCLK, SRC1, SRC2, MRESULT, NZEXP, OUT);
module SFPU_MUL ( BCLK, SRC1, SRC2, NZEXP, OUT);
 
 
        input                   BCLK;
        input                   BCLK;
        input   [31:0]   SRC1,SRC2;      // only exponent of input data used
        input   [31:0]   SRC1,SRC2;      // only exponent of input data used
        input   [47:0]   MRESULT;
 
        input    [2:1]  NZEXP;          // Flags of input data
        input    [2:1]  NZEXP;          // Flags of input data
 
 
        output  reg     [36:0]   OUT;            // The result
        output  reg     [36:0]   OUT;            // The result
 
 
 
        wire    [47:0]   mresult;
        wire  [9:0] exponent,expoh,expol;
        wire  [9:0] exponent,expoh,expol;
        wire  [1:0] restlow,resthigh;
        wire  [1:0] restlow,resthigh;
        wire            zero,sign,orlow;
        wire            zero,sign,orlow;
 
 
 
        assign mresult = {1'b1,SRC1[22:0]} * {1'b1,SRC2[22:0]};   // Unsigned Multiplier
 
 
        assign zero =   ~NZEXP[2] | ~NZEXP[1];  // one of both NULL -> NULL is the result
        assign zero =   ~NZEXP[2] | ~NZEXP[1];  // one of both NULL -> NULL is the result
        assign sign =   (SRC1[31] ^ SRC2[31]) & ~zero;
        assign sign =   (SRC1[31] ^ SRC2[31]) & ~zero;
        assign orlow =  (MRESULT[21:0] != 22'b0);
        assign orlow =  (mresult[21:0] != 22'b0);
 
 
        assign restlow  = {MRESULT[22],orlow};
        assign restlow  = {mresult[22],orlow};
        assign resthigh = {MRESULT[23],(MRESULT[22] | orlow)};
        assign resthigh = {mresult[23],(mresult[22] | orlow)};
 
 
        assign exponent = {2'b00,SRC1[30:23]} + {2'b00,SRC2[30:23]};
        assign exponent = {2'b00,SRC1[30:23]} + {2'b00,SRC2[30:23]};
        assign expoh    = exponent - 10'h07E;
        assign expoh    = exponent - 10'h07E;
        assign expol    = exponent - 10'h07F;    // for MSB if MRESULT=0
        assign expol    = exponent - 10'h07F;    // for MSB if mresult=0
 
 
        always @(posedge BCLK) OUT <= MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}
        always @(posedge BCLK) OUT <= mresult[47] ? {zero,sign,expoh,mresult[46:24],resthigh}
                                                                                          : {zero,sign,expol,MRESULT[45:23],restlow};
                                                                                          : {zero,sign,expol,mresult[45:23],restlow};
 
 
endmodule
endmodule
 
 
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
//
//      4. SP_FPU               Top Level of Single Precision Floating Point Unit
//      4. SP_FPU               Top Level of Single Precision Floating Point Unit
//
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module SP_FPU (BCLK, START, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
module SP_FPU (BCLK, START, OPCODE, SRC1, SRC2, FSR, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);
 
 
        input                   BCLK;           // is not used !
        input                   BCLK;           // is not used !
        input                   START;
        input                   START;
        input    [7:0]   OPCODE;
        input    [7:0]   OPCODE;
        input   [31:0]   SRC1,SRC2;      // Input data
        input   [31:0]   SRC1,SRC2;      // Input data
        input    [8:3]  FSR;            // Floating Point Status Register
        input    [8:3]  FSR;            // Floating Point Status Register
        input   [47:0]   MRESULT;        // Multiplier result
 
        input    [1:0]   BWD;            // Size of integer
        input    [1:0]   BWD;            // Size of integer
        input                   FL;
        input                   FL;
 
 
        output  [31:0]   FP_OUT,I_OUT;   // The results
        output  [31:0]   FP_OUT,I_OUT;   // The results
        output   [4:0]   TT_SP;          // Trap-Type
        output   [4:0]   TT_SP;          // Trap-Type
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        // 001 : ADDF,... + 011 : CMPF
        // 001 : ADDF,... + 011 : CMPF
        SFPU_ADDSUB IADDSUB     ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .BWD(BWD),
        SFPU_ADDSUB IADDSUB     ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .BWD(BWD),
                                                  .SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );
                                                  .SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );
 
 
        // 100 : MULF
        // 100 : MULF
        SFPU_MUL IMUL ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .MRESULT(MRESULT), .OUT(mulout), .NZEXP(nzexp) );
        SFPU_MUL IMUL ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .OUT(mulout) );
 
 
        // FP - Pfad : selection of result and rounding :
        // FP - Pfad : selection of result and rounding :
 
 
        assign fpout = (OPCODE[5] & OPCODE[3]) ? mulout : addout;
        assign fpout = (OPCODE[5] & OPCODE[3]) ? mulout : addout;
 
 

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