| Line 37... |
Line 37... |
// 2. PROG_COUNTER Program Counters
|
// 2. PROG_COUNTER Program Counters
|
// 3. REG_LIST Register List Evaluation
|
// 3. REG_LIST Register List Evaluation
|
// 4. ILL_UNDEF Illegal and Undefined Opcodes Detection
|
// 4. ILL_UNDEF Illegal and Undefined Opcodes Detection
|
// 5. GRUPPE_2 Decoder and State Machine for GRUPPE_2 Opcodes
|
// 5. GRUPPE_2 Decoder and State Machine for GRUPPE_2 Opcodes
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 1. OPDEC_REG Central Instruction Register
|
// 1. OPDEC_REG Central Instruction Register
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module OPDEC_REG ( BCLK, BRESET, NEW, ACC_STAT, PROT_ERROR, ALSB, USED, IC_DIN, IC_INIT, DC_INIT, Y_
|
module OPDEC_REG ( BCLK, BRESET, NEW, ACC_STAT, PROT_ERROR, ALSB, USED, IC_DIN, IC_INIT, DC_INIT, Y_INIT, RESTART, STOP_IC,
|
OPREG, ANZ_VAL, IC_READ, NEW_PC, NEXT_ADR, DATA_HOLD, ABORT, IC_TEX, INIT_DONE);
|
OPREG, ANZ_VAL, IC_READ, NEW_PC, NEXT_ADR, DATA_HOLD, ABORT, IC_TEX, INIT_DONE);
|
|
|
input BCLK,BRESET;
|
input BCLK,BRESET;
|
input NEW; // a program jump took place
|
input NEW; // a program jump took place
|
input [3:0] ACC_STAT; // ICACHE signals data is available or Abort
|
input [3:0] ACC_STAT; // ICACHE signals data is available or Abort
|
| Line 96... |
Line 96... |
|
|
always @(posedge BCLK or negedge BRESET) // is kept until DECODER really needs the data !
|
always @(posedge BCLK or negedge BRESET) // is kept until DECODER really needs the data !
|
if (!BRESET) ABORT <= 1'b0;
|
if (!BRESET) ABORT <= 1'b0;
|
else ABORT <= (acc_err & ~(new_restart | pre_new)) | (ABORT & ~NEW_PC);
|
else ABORT <= (acc_err & ~(new_restart | pre_new)) | (ABORT & ~NEW_PC);
|
|
|
always @(posedge BCLK) if (acc_err) IC_TEX <= (ACC_STAT[3] | PROT_ERROR) ? {nseq_flag,2'b11} : {nse
|
always @(posedge BCLK) if (acc_err) IC_TEX <= (ACC_STAT[3] | PROT_ERROR) ? {nseq_flag,2'b11} : {nseq_flag,~ACC_STAT[2],ACC_STAT[2]};
|
|
|
always @(posedge BCLK) nseq_flag <= NEW_PC | (nseq_flag & ~acc_ok); // for MMU Status Register
|
always @(posedge BCLK) nseq_flag <= NEW_PC | (nseq_flag & ~acc_ok); // for MMU Status Register
|
|
|
always @(posedge BCLK) abort_flag <= acc_err;
|
always @(posedge BCLK) abort_flag <= acc_err;
|
assign acc_ende = ~IC_READ | acc_ok | abort_flag; // abort_flag one cycle later is ok ! If no ICach
|
assign acc_ende = ~IC_READ | acc_ok | abort_flag; // abort_flag one cycle later is ok ! If no ICache access always end
|
|
|
assign new_restart = NEW | RESTART; // They are pulses
|
assign new_restart = NEW | RESTART; // They are pulses
|
|
|
// Branch work out : NEW/RESTART notice if access still not ended
|
// Branch work out : NEW/RESTART notice if access still not ended
|
always @(posedge BCLK) pre_new <= (new_restart & ~acc_ende) | (pre_new & ~acc_ende & BRESET);
|
always @(posedge BCLK) pre_new <= (new_restart & ~acc_ende) | (pre_new & ~acc_ende & BRESET);
|
|
|
assign NEW_PC = (new_restart | pre_new) & acc_ende; // At the end of access geenerate new address !
|
assign NEW_PC = (new_restart | pre_new) & acc_ende; // At the end of access geenerate new address !
|
|
|
// There are 2 "NEW/RESTART" : "new_restart" combinatorical out of DECODER, "pre_new" out of Regist
|
// There are 2 "NEW/RESTART" : "new_restart" combinatorical out of DECODER, "pre_new" out of Register
|
always @(posedge BCLK) new_reg <= new_restart | pre_new | (new_reg & ~acc_ende & BRESET);
|
always @(posedge BCLK) new_reg <= new_restart | pre_new | (new_reg & ~acc_ende & BRESET);
|
|
|
always @(USED or OPREG) // Data first shift to the right
|
always @(USED or OPREG) // Data first shift to the right
|
case (USED)
|
case (USED)
|
3'b000 : data_to_ri = OPREG;
|
3'b000 : data_to_ri = OPREG;
|
| Line 153... |
Line 153... |
4'b00_0_x : ANZ_VAL <= new_anz;
|
4'b00_0_x : ANZ_VAL <= new_anz;
|
4'b00_1_0 : ANZ_VAL <= new_anz + 3'b100;
|
4'b00_1_0 : ANZ_VAL <= new_anz + 3'b100;
|
4'b00_1_1 : ANZ_VAL <= new_anz;
|
4'b00_1_1 : ANZ_VAL <= new_anz;
|
endcase
|
endcase
|
|
|
assign NEXT_ADR = new_reg ? (acc_ok & ~pre_new) : (acc_ok & ~new_anz[2]); // switches MUX at PC res
|
assign NEXT_ADR = new_reg ? (acc_ok & ~pre_new) : (acc_ok & ~new_anz[2]); // switches MUX at PC resp. ICACHE
|
|
|
// Instruction CACHE Control : READ is coming after all INITs are done
|
// Instruction CACHE Control : READ is coming after all INITs are done
|
|
|
always @(posedge BCLK) old_init <= IC_INIT | DC_INIT | Y_INIT;
|
always @(posedge BCLK) old_init <= IC_INIT | DC_INIT | Y_INIT;
|
|
|
| Line 165... |
Line 165... |
|
|
always @(posedge BCLK or negedge BRESET)
|
always @(posedge BCLK or negedge BRESET)
|
if (!BRESET) stop_init <= 1'b0;
|
if (!BRESET) stop_init <= 1'b0;
|
else stop_init <= stop_init | IC_READ;
|
else stop_init <= stop_init | IC_READ;
|
|
|
// The INIT_DONE should come after Reset. But it comes too at LMR PTB therefore extra enable after
|
// The INIT_DONE should come after Reset. But it comes too at LMR PTB therefore extra enable after Reset !
|
always @(posedge BCLK or negedge BRESET)
|
always @(posedge BCLK or negedge BRESET)
|
if (!BRESET) IC_READ <= 1'b0;
|
if (!BRESET) IC_READ <= 1'b0;
|
else IC_READ <= (IC_READ & ~acc_err & ~(STOP_IC & acc_ok)) | NEW_PC | (INIT_DONE & ~stop_init);
|
else IC_READ <= (IC_READ & ~acc_err & ~(STOP_IC & acc_ok)) | NEW_PC | (INIT_DONE & ~stop_init);
|
|
|
// The Opcode-Register can not store the data : keep them in ICACHE at IO-access
|
// The Opcode-Register can not store the data : keep them in ICACHE at IO-access
|
assign DATA_HOLD = ~new_restart & ~new_reg & acc_ok & new_anz[2];
|
assign DATA_HOLD = ~new_restart & ~new_reg & acc_ok & new_anz[2];
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 2. PROG_COUNTER Program Counters
|
// 2. PROG_COUNTER Program Counters
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module PROG_COUNTER ( BCLK, BRESET, NEW, LOAD_PC, NEW_PC, NEXT_ADR, NEXT_PCA, DISP, PC_NEW, USED, US
|
module PROG_COUNTER ( BCLK, BRESET, NEW, LOAD_PC, NEW_PC, NEXT_ADR, NEXT_PCA, DISP, PC_NEW, USED, USER, SAVE_PC, FPU_TRAP,
|
ADIVAR, PC_ARCHI, PC_ICACHE, PC_SAVE, ALSB, IC_USER);
|
ADIVAR, PC_ARCHI, PC_ICACHE, PC_SAVE, ALSB, IC_USER);
|
|
|
input BCLK,BRESET;
|
input BCLK,BRESET;
|
input NEW;
|
input NEW;
|
input LOAD_PC;
|
input LOAD_PC;
|
| Line 237... |
Line 237... |
always @(posedge BCLK or negedge BRESET)
|
always @(posedge BCLK or negedge BRESET)
|
if (!BRESET) pc_ic_reg <= 32'h0;
|
if (!BRESET) pc_ic_reg <= 32'h0;
|
else
|
else
|
pc_ic_reg <= pc_icache_i;
|
pc_ic_reg <= pc_icache_i;
|
|
|
// NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and ther
|
// NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and therefore NEW_PC
|
// is used to initiate a new access in ICACHE
|
// is used to initiate a new access in ICACHE
|
assign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2'b00} +
|
assign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2'b00} + 32'h0000_0004) : pc_ic_reg);
|
|
|
// This MUX is extra for LMR IVAR,... and CINV build in
|
// This MUX is extra for LMR IVAR,... and CINV build in
|
assign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]),pc_icache_i[3:0]};
|
assign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]),pc_icache_i[3:0]};
|
|
|
assign ALSB = pc_ic_reg[1:0]; // for OPDEC_REG
|
assign ALSB = pc_ic_reg[1:0]; // for OPDEC_REG
|
| Line 254... |
Line 254... |
else
|
else
|
if (NEW_PC) IC_USER <= USER;
|
if (NEW_PC) IC_USER <= USER;
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 3. REG_LIST Register List Evaluation
|
// 3. REG_LIST Register List Evaluation
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module REG_LIST ( DIN, IPOS, INIT, OPOS, VALID);
|
module REG_LIST ( DIN, IPOS, INIT, OPOS, VALID);
|
|
|
// Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT
|
// Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT
|
|
|
input [7:0] DIN;
|
input [7:0] DIN;
|
| Line 296... |
Line 296... |
assign OPOS[0] = ~mdat_2[0];
|
assign OPOS[0] = ~mdat_2[0];
|
assign VALID = (mdat_2 != 2'b00);
|
assign VALID = (mdat_2 != 2'b00);
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 4. ILL_UNDEF Illegal and Undefined Opcodes Detection
|
// 4. ILL_UNDEF Illegal and Undefined Opcodes Detection
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module ILL_UNDEF (OPREG, ANZ_VAL, USER, CFG, ILL, UNDEF );
|
module ILL_UNDEF (OPREG, ANZ_VAL, USER, CFG, ILL, UNDEF );
|
|
|
input [23:0] OPREG;
|
input [23:0] OPREG;
|
input [2:0] ANZ_VAL;
|
input [2:0] ANZ_VAL;
|
input [3:1] CFG; // 3=CUSTOM,2=MMU,1=FPU
|
input [3:1] CFG; // 3=CUSTOM,2=MMU,1=FPU
|
| Line 324... |
Line 324... |
|
|
parameter udef_amode = 5'b10011; // Undefined Addressing Mode
|
parameter udef_amode = 5'b10011; // Undefined Addressing Mode
|
parameter imode = 5'b10100; // Immediate Addressing Mode
|
parameter imode = 5'b10100; // Immediate Addressing Mode
|
|
|
// [2]= minimum 3, [1]= minimum 2, [0]=minimum 1
|
// [2]= minimum 3, [1]= minimum 2, [0]=minimum 1
|
assign valid = {(ANZ_VAL[2] | (ANZ_VAL[1:0] == 2'b11)),(ANZ_VAL[2:1] != 2'b00),(ANZ_VAL != 3'b000)}
|
assign valid = {(ANZ_VAL[2] | (ANZ_VAL[1:0] == 2'b11)),(ANZ_VAL[2:1] != 2'b00),(ANZ_VAL != 3'b000)};
|
assign lsbes = (OPREG[1:0] == 2'b10); // Tag of all 3 Byte opcodes
|
assign lsbes = (OPREG[1:0] == 2'b10); // Tag of all 3 Byte opcodes
|
|
|
// +++++++++++++++++++++++++ Detect illegale opcodes +++++++++++++++++++
|
// +++++++++++++++++++++++++ Detect illegale opcodes +++++++++++++++++++
|
|
|
always @(OPREG or lsbes or valid or USER)
|
always @(OPREG or lsbes or valid or USER)
|
| Line 353... |
Line 353... |
16'bx1x_xx_x100_0111_110 : undef_opc = 1'b1; // Format 3 : 1000
|
16'bx1x_xx_x100_0111_110 : undef_opc = 1'b1; // Format 3 : 1000
|
16'b1xx_1x_xxxx_0000_111 : undef_opc = 1'b1; // Format 5 : 1xxx
|
16'b1xx_1x_xxxx_0000_111 : undef_opc = 1'b1; // Format 5 : 1xxx
|
16'b1xx_01_xxxx_0000_111 : undef_opc = 1'b1; // Format 5 : 01xx
|
16'b1xx_01_xxxx_0000_111 : undef_opc = 1'b1; // Format 5 : 01xx
|
16'b1xx_01_00xx_0100_111 : undef_opc = 1'b1; // Format 6 : 0100
|
16'b1xx_01_00xx_0100_111 : undef_opc = 1'b1; // Format 6 : 0100
|
16'b1xx_10_10xx_x100_111 : undef_opc = 1'b1; // Format 6/7 : 1010
|
16'b1xx_10_10xx_x100_111 : undef_opc = 1'b1; // Format 6/7 : 1010
|
16'b1xx_xx_xxxx_x011_111 : undef_opc = ~CFG[1]; // Format 9/11 : FPU Befehle wie MOVif etc. und
|
16'b1xx_xx_xxxx_x011_111 : undef_opc = ~CFG[1]; // Format 9/11 : FPU Befehle wie MOVif etc. und ADDf etc.
|
16'b1xx_xx_xxxx_1111_111 : undef_opc = ~CFG[1]; // Format 12 : FPU Befehle wie POLYf etc.
|
16'b1xx_xx_xxxx_1111_111 : undef_opc = ~CFG[1]; // Format 12 : FPU Befehle wie POLYf etc.
|
16'b1xx_x1_xxxx_0001_111 : undef_opc = 1'b1; // Format 14 : x1xx
|
16'b1xx_x1_xxxx_0001_111 : undef_opc = 1'b1; // Format 14 : x1xx
|
16'b1xx_10_00xx_0001_111 : undef_opc = 1'b1; // Format 14 : 1000
|
16'b1xx_10_00xx_0001_111 : undef_opc = 1'b1; // Format 14 : 1000
|
16'b1xx_10_1xxx_0001_111 : undef_opc = 1'b1; // Format 14 : 101x
|
16'b1xx_10_1xxx_0001_111 : undef_opc = 1'b1; // Format 14 : 101x
|
16'b1xx_00_1xxx_0001_111 : undef_opc = ~CFG[2] | ~OPREG[18]; // Format 14 : LMR/SMR
|
16'b1xx_00_1xxx_0001_111 : undef_opc = ~CFG[2] | ~OPREG[18]; // Format 14 : LMR/SMR
|
| Line 379... |
Line 379... |
assign gen22 = (OPREG[10:6] == udef_amode);
|
assign gen22 = (OPREG[10:6] == udef_amode);
|
assign gen13 = (OPREG[23:19] == udef_amode);
|
assign gen13 = (OPREG[23:19] == udef_amode);
|
assign gen23 = (OPREG[18:14] == udef_amode);
|
assign gen23 = (OPREG[18:14] == udef_amode);
|
|
|
always @(OPREG or valid or gen12 or gen22 or gen13 or gen23)
|
always @(OPREG or valid or gen12 or gen22 or gen13 or gen23)
|
if (valid[2] && (OPREG[7:5] != 3'b000) && (OPREG[3:0] == 4'b1110)) undef_am = gen13 | gen23; // ne
|
if (valid[2] && (OPREG[7:5] != 3'b000) && (OPREG[3:0] == 4'b1110)) undef_am = gen13 | gen23; // nearly all 3 Byte opcodes
|
else
|
else
|
undef_am = valid[1] & gen12 & (OPREG[1:0] != 2'b10) & ((OPREG[3:2] != 2'b11) & gen22); // all
|
undef_am = valid[1] & gen12 & (OPREG[1:0] != 2'b10) & ((OPREG[3:2] != 2'b11) & gen22); // all 2 Byte opcodes
|
|
|
// 3. When is Immediate not allowed ?
|
// 3. When is Immediate not allowed ?
|
|
|
assign igen12 = (OPREG[15:11] == imode);
|
assign igen12 = (OPREG[15:11] == imode);
|
assign igen22 = (OPREG[10:6] == imode);
|
assign igen22 = (OPREG[10:6] == imode);
|
assign igen13 = (OPREG[23:19] == imode);
|
assign igen13 = (OPREG[23:19] == imode);
|
assign igen23 = (OPREG[18:14] == imode);
|
assign igen23 = (OPREG[18:14] == imode);
|
|
|
always @(*)
|
always @(*)
|
casex ({valid[2:1],OPREG[13:2],lsbes})
|
casex ({valid[2:1],OPREG[13:2],lsbes})
|
15'bx1_xxxxxx_x0xx11_0 : undef_im = igen12 & (OPREG[5:4] != 2'b01); // Format 2 : ADDQD,SPR,Sco
|
15'bx1_xxxxxx_x0xx11_0 : undef_im = igen12 & (OPREG[5:4] != 2'b01); // Format 2 : ADDQD,SPR,Scond
|
15'bx1_xxxxxx_x10111_0 : undef_im = igen12; // Format 2 : ACB,MOVQ
|
15'bx1_xxxxxx_x10111_0 : undef_im = igen12; // Format 2 : ACB,MOVQ
|
15'bx1_xxxxx0_011111_0 : undef_im = igen12; // Format 3 : CXPD,JUMP,JSR
|
15'bx1_xxxxx0_011111_0 : undef_im = igen12; // Format 3 : CXPD,JUMP,JSR
|
15'bx1_xxxxxx_xxxxx0_0 : undef_im = igen22; // Format 4
|
15'bx1_xxxxxx_xxxxx0_0 : undef_im = igen22; // Format 4
|
15'bx1_xxxxxx_xxxx01_0 : undef_im = (igen12 & (OPREG[5:4] == 2'b10)) // Format 4 : SRC1 - not AD
|
15'bx1_xxxxxx_xxxx01_0 : undef_im = (igen12 & (OPREG[5:4] == 2'b10)) // Format 4 : SRC1 - not ADDR
|
|(igen22 & (OPREG[5:4] != 2'b00)); // Format 4 : SRC2 - CMP
|
|(igen22 & (OPREG[5:4] != 2'b00)); // Format 4 : SRC2 - CMP
|
15'b1x_xxxxxx_x10011_1 : undef_im = igen23; // Format 6+7
|
15'b1x_xxxxxx_x10011_1 : undef_im = igen23; // Format 6+7
|
15'b1x_xxx0xx_0x1011_1 : undef_im = igen13 | igen23; // Format 8 EXT,CVTP
|
15'b1x_xxx0xx_0x1011_1 : undef_im = igen13 | igen23; // Format 8 EXT,CVTP
|
15'b1x_xxx0xx_101011_1 : undef_im = igen23; // Format 8 : INS
|
15'b1x_xxx0xx_101011_1 : undef_im = igen23; // Format 8 : INS
|
15'b1x_xxx0xx_111011_1 : undef_im = igen13; // Format 8 : CHECK
|
15'b1x_xxx0xx_111011_1 : undef_im = igen13; // Format 8 : CHECK
|
| Line 418... |
Line 418... |
|
|
assign UNDEF = undef_opc | undef_am | undef_im;
|
assign UNDEF = undef_opc | undef_am | undef_im;
|
|
|
endmodule
|
endmodule
|
|
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
//
|
//
|
// 5. GRUPPE_2 Decoder and State Machine for GRUPPE_2 Opcodes
|
// 5. GRUPPE_2 Decoder and State Machine for GRUPPE_2 Opcodes
|
//
|
//
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
module GRUPPE_2 ( BCLK, PHASE_0, OPREG, PHASE, SRC_1, SRC_2, REGA1, REGA2, IRRW1, IRRW2, ADRD1, ADRD
|
module GRUPPE_2 ( BCLK, PHASE_0, OPREG, PHASE, SRC_1, SRC_2, REGA1, REGA2, IRRW1, IRRW2, ADRD1, ADRD2, EXR12, EXR22,
|
PHRD1, PHRD2, NXRD1, NXRW2, ACCA, OPERA,
|
PHRD1, PHRD2, NXRD1, NXRW2, ACCA, OPERA,
|
STATE_0, STATE_GROUP_50, STATE_GROUP_60 );
|
STATE_0, STATE_GROUP_50, STATE_GROUP_60 );
|
|
|
|
|
input BCLK,PHASE_0;
|
input BCLK,PHASE_0;
|
| Line 470... |
Line 470... |
// Address-Field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
|
// Address-Field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
|
parameter addr_nop = 19'h0; // alle Parameter auf 0
|
parameter addr_nop = 19'h0; // alle Parameter auf 0
|
parameter disp2ea = 19'bxx_0010_0000_0_0000_0010; // pass DISP
|
parameter disp2ea = 19'bxx_0010_0000_0_0000_0010; // pass DISP
|
parameter case_op = 19'bxx_0010_1000_0_0000_0001; // SRC1 add to PC_ARCHI
|
parameter case_op = 19'bxx_0010_1000_0_0000_0001; // SRC1 add to PC_ARCHI
|
parameter read_byb = 19'b00_1011_11xx_0_0000_0011; // read of SRC2 for Bit opcodes
|
parameter read_byb = 19'b00_1011_11xx_0_0000_0011; // read of SRC2 for Bit opcodes
|
parameter exr11 = {2'b10 ,4'b1011,4'h0 ,9'h080}; // 2. access External with Mem.-Pointer + 4* Dis
|
parameter exr11 = {2'b10 ,4'b1011,4'h0 ,9'h080}; // 2. access External with Mem.-Pointer + 4* Disp
|
parameter adrcvtp = 19'bxx_0010_0111_0_0000_0000; // for CVTP
|
parameter adrcvtp = 19'bxx_0010_0111_0_0000_0000; // for CVTP
|
parameter addone = 19'bxx_0010_0100_0_0000_0000; // for INDEX : SRC1 + SRC2 , simple Add without Fl
|
parameter addone = 19'bxx_0010_0100_0_0000_0000; // for INDEX : SRC1 + SRC2 , simple Add without Flags
|
parameter addind = 19'bxx_0010_0100_0_0000_0011; // for INDEX : SRC1 + EA
|
parameter addind = 19'bxx_0010_0100_0_0000_0011; // for INDEX : SRC1 + EA
|
parameter src_x = 7'hxx;
|
parameter src_x = 7'hxx;
|
parameter dest_x = 6'hxx;
|
parameter dest_x = 6'hxx;
|
parameter imme = {1'b1,6'hxx};
|
parameter imme = {1'b1,6'hxx};
|
parameter F0 = 7'h20;
|
parameter F0 = 7'h20;
|
| Line 558... |
Line 558... |
assign phchk = {7'b0101_010,size_dw}; // Phase 54 or 55
|
assign phchk = {7'b0101_010,size_dw}; // Phase 54 or 55
|
|
|
assign op_kust = {1'bx,OPERA[9:8],8'h7A}; // Special-Opcode for MOVM/CMPM
|
assign op_kust = {1'bx,OPERA[9:8],8'h7A}; // Special-Opcode for MOVM/CMPM
|
assign op_bwd = {1'bx,OPERA[9:8],8'h45}; // for CASE and Bit opcodes
|
assign op_bwd = {1'bx,OPERA[9:8],8'h45}; // for CASE and Bit opcodes
|
|
|
assign re_wr = {EXR22[18:17],4'b0101,4'h0, 9'h003}; // REUSE Address : Write of rmw , top 2 Bits
|
assign re_wr = {EXR22[18:17],4'b0101,4'h0, 9'h003}; // REUSE Address : Write of rmw , top 2 Bits contain size
|
|
|
always @(posedge BCLK) tbit_flag <= ~OPERA[1]; // due to Timing ...
|
always @(posedge BCLK) tbit_flag <= ~OPERA[1]; // due to Timing ...
|
always @(posedge BCLK) size_dw <= OPERA[9];
|
always @(posedge BCLK) size_dw <= OPERA[9];
|
|
|
always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]}; // for CHECK
|
always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]}; // for CHECK
|
| Line 576... |
Line 576... |
assign exoffset = inss_flag ? 19'b10_1011_0000_0_0000_0011 // Read of SRC2 at INSS
|
assign exoffset = inss_flag ? 19'b10_1011_0000_0_0000_0011 // Read of SRC2 at INSS
|
: 19'b10_1011_1100_0_0000_0011; // Read of SRC1+Offset at EXT, SRC2+Offset at INS
|
: 19'b10_1011_1100_0_0000_0011; // Read of SRC1+Offset at EXT, SRC2+Offset at INS
|
|
|
always @(*)
|
always @(*)
|
casex (op_reg)
|
casex (op_reg)
|
5'b1_0000 : // MOVS Phase 0 : Entry 1. Pointer "in Page"-test prepare, 2. test for R0=0 , then jum
|
5'b1_0000 : // MOVS Phase 0 : Entry 1. Pointer "in Page"-test prepare, 2. test for R0=0 , then jump to x'C0
|
begin
|
begin
|
STATE_0 = { addr_nop,8'h67, 7'h01, 7'h02, 1'b0,dest_x,op_stpr, 2'b00,2'b00,4'h0 }; // String
|
STATE_0 = { addr_nop,8'h67, 7'h01, 7'h02, 1'b0,dest_x,op_stpr, 2'b00,2'b00,4'h0 }; // String-Pointer prepare
|
state_50 = dont_care;
|
state_50 = dont_care;
|
state_53 = dont_care;
|
state_53 = dont_care;
|
state_54 = dont_care;
|
state_54 = dont_care;
|
state_55 = dont_care;
|
state_55 = dont_care;
|
state_58 = dont_care;
|
state_58 = dont_care;
|
| Line 594... |
Line 594... |
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_53 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b1,temp_h,op_adr, 2'b00,2'b00,NXRW2 };
|
state_53 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b1,temp_h,op_adr, 2'b00,2'b00,NXRW2 };
|
state_54 = dont_care;
|
state_54 = dont_care;
|
state_55 = dont_care;
|
state_55 = dont_care;
|
state_58 = { disp2ea, 8'h65, src_x, src_x, 1'b1,temp_1,op_adr, 2'b00,2'b00,4'b1110 }; // Read
|
state_58 = { disp2ea, 8'h65, src_x, src_x, 1'b1,temp_1,op_adr, 2'b00,2'b00,4'b1110 }; // Read of DISP for count
|
state_59 = { addr_nop,8'h67, rtmph, rtmp1, 1'b0,dest_x,op_stpr, 2'b00,2'b00,4'h0 }; // String
|
state_59 = { addr_nop,8'h67, rtmph, rtmp1, 1'b0,dest_x,op_stpr, 2'b00,2'b00,4'h0 }; // String-Pointer prepare
|
state_5A = dont_care;
|
state_5A = dont_care;
|
end
|
end
|
5'b1_0010 : // JUMP/JSR
|
5'b1_0010 : // JUMP/JSR
|
begin
|
begin
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
| Line 624... |
Line 624... |
end
|
end
|
5'b1_1111 : // RDVAL+WRVAL
|
5'b1_1111 : // RDVAL+WRVAL
|
begin
|
begin
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_53 = { addr_nop,8'h00, src_x, src_x, 1'b0,dest_x,op_rwv, 2'b00,2'b10,4'h0 }; // LD_OU
|
state_53 = { addr_nop,8'h00, src_x, src_x, 1'b0,dest_x,op_rwv, 2'b00,2'b10,4'h0 }; // LD_OUT set because of "F"
|
state_54 = dont_care;
|
state_54 = dont_care;
|
state_55 = dont_care;
|
state_55 = dont_care;
|
state_58 = dont_care;
|
state_58 = dont_care;
|
state_59 = dont_care;
|
state_59 = dont_care;
|
state_5A = dont_care;
|
state_5A = dont_care;
|
| Line 636... |
Line 636... |
5'b1_0011 : // CASE
|
5'b1_0011 : // CASE
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { case_op, 8'h54, SRC_1, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h0 };
|
: { case_op, 8'h54, SRC_1, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h0 };
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // only
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // only one operand in mem.
|
state_53 = { case_op, 8'h54, imme, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h0 };
|
state_53 = { case_op, 8'h54, imme, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h0 };
|
state_54 = { addr_nop,8'h66, src_x, src_x, 1'b1,temp_h,op_adr, 2'b00,2'b00,4'h0 };
|
state_54 = { addr_nop,8'h66, src_x, src_x, 1'b1,temp_h,op_adr, 2'b00,2'b00,4'h0 };
|
state_55 = dont_care;
|
state_55 = dont_care;
|
state_58 = dont_care;
|
state_58 = dont_care;
|
state_59 = dont_care;
|
state_59 = dont_care;
|
state_5A = dont_care;
|
state_5A = dont_care;
|
end
|
end
|
5'b1_0100 : // all Bit opcodes with Bit in memory. RMW Test in Phase x'59 = Special case, otherwis
|
5'b1_0100 : // all Bit opcodes with Bit in memory. RMW Test in Phase x'59 = Special case, otherwise x'58
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_50 = ACCA[3] ? // _M...
|
state_50 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_54 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }; // here S
|
state_54 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }; // here SRC1 => TEMP_H
|
state_55 = dont_care;
|
state_55 = dont_care;
|
state_58 = { read_byb,8'h59, rtmph, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h1 }; // next re
|
state_58 = { read_byb,8'h59, rtmph, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h1 }; // next read of Byte
|
state_59 = tbit_flag ?
|
state_59 = tbit_flag ?
|
{ addr_nop,8'h00, src_x, imme, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 } // TBIT end
|
{ addr_nop,8'h00, src_x, imme, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 } // TBIT end
|
: { re_wr, 8'h27, src_x, imme, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 }; // CBIT/SBIT/IBIT
|
: { re_wr, 8'h27, src_x, imme, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 }; // CBIT/SBIT/IBIT end
|
state_5A = dont_care;
|
state_5A = dont_care;
|
end
|
end
|
5'b1_0101 : // EXTS : BASE Operand => TEMP, calculate address of Destination
|
5'b1_0101 : // EXTS : BASE Operand => TEMP, calculate address of Destination
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
| Line 671... |
Line 671... |
state_50 = ACCA[3] ? // _M...
|
state_50 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_54 = ACCA[1] ?
|
state_54 = ACCA[1] ?
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here Adr(DEST)
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here Adr(DEST) => EA
|
: { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immedi
|
: { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immediate read
|
state_55 = dont_care;
|
state_55 = dont_care;
|
state_58 = { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte
|
state_58 = { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immediate read
|
state_59 = ACCA[1] ? // _..M.
|
state_59 = ACCA[1] ? // _..M.
|
{ re_wr, 8'h27, imme, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
|
{ re_wr, 8'h27, imme, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
|
: { addr_nop,8'h00, imme, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Regi
|
: { addr_nop,8'h00, imme, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
|
state_5A = dont_care;
|
state_5A = dont_care;
|
end
|
end
|
5'b1_1010 : // EXT : BASE Operand => TEMP, calculate address of Destination
|
5'b1_1010 : // EXT : BASE Operand => TEMP, calculate address of Destination
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_50 = ACCA[3] ? // _M...
|
state_50 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Addr =
|
state_53 = { addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Addr => EA Reg
|
state_54 = ACCA[1] ?
|
state_54 = ACCA[1] ?
|
( ACCA[3] ?
|
( ACCA[3] ?
|
{addr_nop,8'h5A, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }
|
{addr_nop,8'h5A, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }
|
:{ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } ) // here Adr(DEST)
|
:{ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } ) // here Adr(DEST) => EA
|
: { addr_nop,8'h59, rd_reg,(ACCA[3] ? imme : rtmph),
|
: { addr_nop,8'h59, rd_reg,(ACCA[3] ? imme : rtmph),
|
1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
|
1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
|
state_55 = { exoffset,8'h54, rd_reg,src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h1 }; // Read S
|
state_55 = { exoffset,8'h54, rd_reg,src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h1 }; // Read Source, EA reuse
|
state_58 = { addr_nop,8'h59, rd_reg,rtmph, 1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displac
|
state_58 = { addr_nop,8'h59, rd_reg,rtmph, 1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
|
state_59 = ACCA[1] ? // _..M.
|
state_59 = ACCA[1] ? // _..M.
|
{ re_wr, 8'h27, src_x, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
|
{ re_wr, 8'h27, src_x, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
|
: { addr_nop,8'h00, src_x, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Regi
|
: { addr_nop,8'h00, src_x, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
|
state_5A = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }; // special
|
state_5A = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }; // special case Mem-Mem
|
end
|
end
|
5'b1_1011 : // INS/INSS : BASE Operand => TEMP, SRC2 read as Double ! RMW not tested (Phase x'6A)
|
5'b1_1011 : // INS/INSS : BASE Operand => TEMP, SRC2 read as Double ! RMW not tested (Phase x'6A) but uncritical
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
|
state_50 = ACCA[3] ? // _M...
|
state_50 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 }; // zext(
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 }; // zext(SRC1) => TEMP
|
state_54 = ACCA[1] ?
|
state_54 = ACCA[1] ?
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here Adr(DEST) =
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here Adr(DEST) => EA
|
: { addr_nop,8'h5A, SRC_2, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,imdi }; // Imme./Disp. r
|
: { addr_nop,8'h5A, SRC_2, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,imdi }; // Imme./Disp. read
|
state_55 = { exoffset,8'h6A, rd_reg,src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h1 }; // Read S
|
state_55 = { exoffset,8'h6A, rd_reg,src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h1 }; // Read Source, EA reuse
|
state_58 = { addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; //
|
state_58 = { addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; //
|
state_59 = ACCA[1] ? // _..M.
|
state_59 = ACCA[1] ? // _..M.
|
{ re_wr, 8'h27, rtmph, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
|
{ re_wr, 8'h27, rtmph, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
|
: { addr_nop,8'h00, rtmph, rtmpl, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Regi
|
: { addr_nop,8'h00, rtmph, rtmpl, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
|
state_5A = { addr_nop,8'h68, imme, src_x, 1'b1,temp_1,op_msk, 2'b00,2'b00,4'h0 }; // Mask ge
|
state_5A = { addr_nop,8'h68, imme, src_x, 1'b1,temp_1,op_msk, 2'b00,2'b00,4'h0 }; // Mask generate
|
end
|
end
|
5'b1_1101 : // INDEX :
|
5'b1_1101 : // INDEX :
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
|
state_50 = ACCA[3] ? // _M...
|
state_50 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 }; // zext(
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 }; // zext(SRC1) => TEMP_H
|
state_54 = ACCA[1] ?
|
state_54 = ACCA[1] ?
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // zext(SRC2) => TE
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // zext(SRC2) => TEMP_L
|
: { addr_nop,8'h55, SRC_2, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h55, SRC_2, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0 };
|
state_55 = { addr_nop,8'h5A, rd_reg,rtmph, 1'b1,temp_h,op_mul, 2'b00,2'b00,4'h0 }; // Multip
|
state_55 = { addr_nop,8'h5A, rd_reg,rtmph, 1'b1,temp_h,op_mul, 2'b00,2'b00,4'h0 }; // Multiplication
|
state_58 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0 }; //
|
state_58 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0 }; //
|
state_59 = { addind, 8'h60, rtmpl, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Add of
|
state_59 = { addind, 8'h60, rtmpl, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Add of Index in EA
|
state_5A = { addone, 8'h59, rd_reg,rtmph, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Add of
|
state_5A = { addone, 8'h59, rd_reg,rtmph, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Add of EA (=+1)
|
end
|
end
|
5'b1_0111 : // DEI + MEI , both read 8B from DEST ! RMW critical !
|
5'b1_0111 : // DEI + MEI , both read 8B from DEST ! RMW critical !
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
| Line 748... |
Line 748... |
state_50 = ACCA[3] ? // _M...
|
state_50 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
|
state_54 = ACCA[1] ?
|
state_54 = ACCA[1] ?
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here SRC1 => TE
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here SRC1 => TEMP_H
|
: { addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_x,OPERA, 2'b01,2'b00,4'h0 }; // 1. part of Reg
|
: { addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_x,OPERA, 2'b01,2'b00,4'h0 }; // 1. part of Register
|
state_55 = dont_care;
|
state_55 = dont_care;
|
state_58 = size_dw ?
|
state_58 = size_dw ?
|
{ addr_nop,8'h59, rtmph, imme, 1'b0,dest_x,OPERA, 2'b01,2'b00,4'h0 } // D needs 2 accesse
|
{ addr_nop,8'h59, rtmph, imme, 1'b0,dest_x,OPERA, 2'b01,2'b00,4'h0 } // D needs 2 accesses
|
: { addr_nop,8'h1F, rtmph, imme, 1'b0,dest_x,OPERA, 2'b11,2'b00,4'h0 }; // B+W start at o
|
: { addr_nop,8'h1F, rtmph, imme, 1'b0,dest_x,OPERA, 2'b11,2'b00,4'h0 }; // B+W start at once
|
state_59 = { addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l), // SRC2 = memory or Reg
|
state_59 = { addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l), // SRC2 = memory or Reg
|
~ACCA[1],dest_2,OPERA, 2'b10,2'b00,4'h0 };
|
~ACCA[1],dest_2,OPERA, 2'b10,2'b00,4'h0 };
|
state_5A = dont_care;
|
state_5A = dont_care;
|
end
|
end
|
5'b1_1000 : // CHECK
|
5'b1_1000 : // CHECK
|
begin
|
begin
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // No Re
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // No Register !
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_53 = { addr_nop,phchk, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }; // No Imm
|
state_53 = { addr_nop,phchk, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }; // No Immediate !
|
state_54 = ACCA[1] ?
|
state_54 = ACCA[1] ?
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }
|
: ( size_dw ?
|
: ( size_dw ?
|
{addr_nop,8'h5A, SRC_2, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 } // Upper Bound - point
|
{addr_nop,8'h5A, SRC_2, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 } // Upper Bound - pointer
|
: {addr_nop,8'h00, rtmph, SRC_2, 1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 } );
|
: {addr_nop,8'h00, rtmph, SRC_2, 1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 } );
|
state_55 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 };
|
state_55 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 };
|
state_58 = size_dw ?
|
state_58 = size_dw ?
|
{ addr_nop,8'h59, imme, src_x, 1'b1,temp_1,op_mov, 2'b00,2'b00,4'h0 } // here SRC2 => TEM
|
{ addr_nop,8'h59, imme, src_x, 1'b1,temp_1,op_mov, 2'b00,2'b00,4'h0 } // here SRC2 => TEMP_1
|
: { addr_nop,8'h00, rtmph, imme, 1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 };
|
: { addr_nop,8'h00, rtmph, imme, 1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 };
|
state_59 = { addr_nop,8'h5A, rtmp1, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 }; // Upper Bo
|
state_59 = { addr_nop,8'h5A, rtmp1, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 }; // Upper Bound - pointer
|
state_5A = { addr_nop,8'h00, rtmph, (ACCA[1] ? rtmp1 : SRC_2),
|
state_5A = { addr_nop,8'h00, rtmph, (ACCA[1] ? rtmp1 : SRC_2),
|
1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 }; // pointer - Lower Bound
|
1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 }; // pointer - Lower Bound
|
end
|
end
|
5'b1_1100 : // CVTP
|
5'b1_1100 : // CVTP
|
begin
|
begin
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // Addre
|
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // Address
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
|
state_53 = { addr_nop,8'h54, src_x, src_x, 1'b1,temp_h,op_adr, 2'b00,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, src_x, src_x, 1'b1,temp_h,op_adr, 2'b00,2'b00,4'h0 };
|
state_54 = { adrcvtp, 8'h73, rtmph, rd_reg,1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // 8*TEMP
|
state_54 = { adrcvtp, 8'h73, rtmph, rd_reg,1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // 8*TEMP+Offset
|
state_55 = dont_care;
|
state_55 = dont_care;
|
state_58 = dont_care;
|
state_58 = dont_care;
|
state_59 = dont_care;
|
state_59 = dont_care;
|
state_5A = dont_care;
|
state_5A = dont_care;
|
end
|
end
|
| Line 799... |
Line 799... |
: { addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,get8b_s };
|
state_53 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,get8b_s };
|
state_54 = ACCA[1] ?
|
state_54 = ACCA[1] ?
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_trul, 2'b00,2'b00,NXRW2 }
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_trul, 2'b00,2'b00,NXRW2 }
|
: { addr_nop,8'h5A, src_x, src_x, 1'b0,temp_h,op_trul, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h5A, src_x, src_x, 1'b0,temp_h,op_trul, 2'b00,2'b00,4'h0 };
|
state_55 = { addr_nop,8'h54, rtmph, imme, 1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 }; // 2. hal
|
state_55 = { addr_nop,8'h54, rtmph, imme, 1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 }; // 2. half of external SRC1
|
state_58 = { addr_nop,8'h59, rtmph, imme, 1'b0,dest_2,OPERA, 2'b01,2'b00,4'h0 };
|
state_58 = { addr_nop,8'h59, rtmph, imme, 1'b0,dest_2,OPERA, 2'b01,2'b00,4'h0 };
|
state_59 = { addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),
|
state_59 = { addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),
|
~ACCA[1],dest_2,OPERA, 2'b10,2'b00,4'h0 };
|
~ACCA[1],dest_2,OPERA, 2'b10,2'b00,4'h0 };
|
state_5A = { addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_2,OPERA, 2'b01,2'b00,4'h0 }; // empty cy
|
state_5A = { addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_2,OPERA, 2'b01,2'b00,4'h0 }; // empty cycle for TRUNC => TEMP !
|
end
|
end
|
5'b01_001 : // SCALBF : RMW critical !
|
5'b01_001 : // SCALBF : RMW critical !
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
| Line 873... |
Line 873... |
: { addr_nop,8'h59, imme, SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_s };
|
: { addr_nop,8'h59, imme, SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_s };
|
state_54 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 };
|
state_54 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 };
|
state_55 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
|
state_55 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
|
state_58 = { addr_nop,8'h59, (ACCA[3] ? rtmph : SRC_1), //_M...
|
state_58 = { addr_nop,8'h59, (ACCA[3] ? rtmph : SRC_1), //_M...
|
imme, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_d };
|
imme, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_d };
|
state_59 = { addr_nop,8'h5A, (ACCA[3] ? (ACCA[1] ? rtmpl : imme) : src_1l), (ACCA[1] ? imme :
|
state_59 = { addr_nop,8'h5A, (ACCA[3] ? (ACCA[1] ? rtmpl : imme) : src_1l), (ACCA[1] ? imme : src_2l),
|
1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0 };
|
1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0 };
|
state_5A = { addr_nop,8'h61, rtmph, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
|
state_5A = { addr_nop,8'h61, rtmph, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
|
end
|
end
|
5'b01_111 : // DOTF
|
5'b01_111 : // DOTF
|
begin
|
begin
|
| Line 914... |
Line 914... |
|
|
always @(*)
|
always @(*)
|
casex (PHASE)
|
casex (PHASE)
|
4'h0 : STATE_GROUP_50 = state_50;
|
4'h0 : STATE_GROUP_50 = state_50;
|
// Phase 51 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
|
// Phase 51 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
|
4'h1 : STATE_GROUP_50 = {exr11, 8'h52, src_x,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111}
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4'h1 : STATE_GROUP_50 = {exr11, 8'h52, src_x,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111};
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// Phase 52 : Memory-Pointer for Memory Relative and last access External
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// Phase 52 : Memory-Pointer for Memory Relative and last access External
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4'h2 : STATE_GROUP_50 = {EXR12, 8'h53, IRRW1,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111}
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4'h2 : STATE_GROUP_50 = {EXR12, 8'h53, IRRW1,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111}; // atys[0] !
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4'h3 : STATE_GROUP_50 = state_53;
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4'h3 : STATE_GROUP_50 = state_53;
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4'h4 : STATE_GROUP_50 = state_54;
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4'h4 : STATE_GROUP_50 = state_54;
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4'h5 : STATE_GROUP_50 = state_55;
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4'h5 : STATE_GROUP_50 = state_55;
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// Phase 56 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
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// Phase 56 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
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4'h6 : STATE_GROUP_50 = {exr11, 8'h57, src_x,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111}
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4'h6 : STATE_GROUP_50 = {exr11, 8'h57, src_x,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111};
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// Phase 57 : Memory-Pointer for Memory Relative and last access External
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// Phase 57 : Memory-Pointer for Memory Relative and last access External
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4'h7 : STATE_GROUP_50 = {EXR22, 8'h58, IRRW2,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111}
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4'h7 : STATE_GROUP_50 = {EXR22, 8'h58, IRRW2,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111}; // atyd[0] !
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4'h8 : STATE_GROUP_50 = state_58;
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4'h8 : STATE_GROUP_50 = state_58;
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4'h9 : STATE_GROUP_50 = state_59;
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4'h9 : STATE_GROUP_50 = state_59;
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4'hA : STATE_GROUP_50 = state_5A;
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4'hA : STATE_GROUP_50 = state_5A;
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default : STATE_GROUP_50 = dont_care;
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default : STATE_GROUP_50 = dont_care;
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endcase
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endcase
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always @(*)
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always @(*)
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casex (PHASE)
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casex (PHASE)
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4'h0 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b1,chkreg,op_adr, 2'b00,2'b00,4'h0 }
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4'h0 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b1,chkreg,op_adr, 2'b00,2'b00,4'h0 }; // for INDEX
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4'h1 : STATE_GROUP_60 = { addr_nop,8'h62, rtmpl, F0, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0 }
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4'h1 : STATE_GROUP_60 = { addr_nop,8'h62, rtmpl, F0, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0 }; // for DOTL
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4'h2 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b0,w_F0_h,op_addl, 2'b00,2'b00,4'h0 }
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4'h2 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b0,w_F0_h,op_addl, 2'b00,2'b00,4'h0 }; // for DOTL & POLYL !
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4'h3 : STATE_GROUP_60 = { addr_nop,8'h00, rtmph, F0, 1'b1,w_F0, op_addf, 2'b00,2'b00,4'h0 }
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4'h3 : STATE_GROUP_60 = { addr_nop,8'h00, rtmph, F0, 1'b1,w_F0, op_addf, 2'b00,2'b00,4'h0 }; // for DOTF
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4'h4 : STATE_GROUP_60 = ACCA[1] ? // ..M.
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4'h4 : STATE_GROUP_60 = ACCA[1] ? // ..M.
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{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,temp_h,op_mull, 2'b00,2'b00,NXRW2 }
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{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,temp_h,op_mull, 2'b00,2'b00,NXRW2 }
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: { addr_nop,8'h59, SRC_2, rtmph, 1'b0,temp_h,op_addl, 2'b01,2'b00,4'h0 }; // for POLYL
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: { addr_nop,8'h59, SRC_2, rtmph, 1'b0,temp_h,op_addl, 2'b01,2'b00,4'h0 }; // for POLYL
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4'h5 : STATE_GROUP_60 = { addr_nop,8'h59, src_x, src_x, 1'b1,temp_l,op_kust, 2'b00,2'b00,4'h0 }
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4'h5 : STATE_GROUP_60 = { addr_nop,8'h59, src_x, src_x, 1'b1,temp_l,op_kust, 2'b00,2'b00,4'h0 }; // for MOVM/CMPM
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4'h6 : STATE_GROUP_60 = { addr_nop,8'h01, rtmph, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 };
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4'h6 : STATE_GROUP_60 = { addr_nop,8'h01, rtmph, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // for JUMP/JSR/CASE
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4'h7 : STATE_GROUP_60 = { addr_nop,8'hC0, (op_reg_reg[0] ? rtmpl : 7'h00), // Jump to Stri
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4'h7 : STATE_GROUP_60 = { addr_nop,8'hC0, (op_reg_reg[0] ? rtmpl : 7'h00), // Jump to String execution
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src_x, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 }; // LD_OUT set, CMPS F-Flag
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src_x, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 }; // LD_OUT set, CMPS F-Flag
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// for INS
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// for INS
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4'h8 : STATE_GROUP_60 = { addr_nop,8'h69, rd_reg,rtmph, 1'b1,temp_h,op_lsh, 2'b00,2'b00,4'h0 };
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4'h8 : STATE_GROUP_60 = { addr_nop,8'h69, rd_reg,rtmph, 1'b1,temp_h,op_lsh, 2'b00,2'b00,4'h0 }; // SRC1 shift
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4'h9 : STATE_GROUP_60 = { addr_nop,8'h59, rd_reg,rtmp1, 1'b0,dest_x,op_lsh, 2'b00,2'b00,4'h0 };
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4'h9 : STATE_GROUP_60 = { addr_nop,8'h59, rd_reg,rtmp1, 1'b0,dest_x,op_lsh, 2'b00,2'b00,4'h0 }; // Mask shift
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4'hA : STATE_GROUP_60 = { addr_nop,8'h5A, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,imdi };
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4'hA : STATE_GROUP_60 = { addr_nop,8'h5A, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,imdi }; // Imme./Disp. read
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// for CXPD, this State is decoded explicitly in DECODER
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// for CXPD, this State is decoded explicitly in DECODER
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4'hB : STATE_GROUP_60 = { addr_nop,8'h39, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 };
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4'hB : STATE_GROUP_60 = { addr_nop,8'h39, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 }; // pass PC
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default : STATE_GROUP_60 = dont_care;
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default : STATE_GROUP_60 = dont_care;
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endcase
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endcase
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endmodule
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endmodule
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