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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: STEUER_MISC.v
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// Filename: STEUER_MISC.v
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// Version: 1.0
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// Version: 1.1 bug fix
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 21 January 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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PHRD1, PHRD2, NXRD1, NXRW2, ACCA, OPERA,
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PHRD1, PHRD2, NXRD1, NXRW2, ACCA, OPERA,
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STATE_0, STATE_GROUP_50, STATE_GROUP_60 );
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STATE_0, STATE_GROUP_50, STATE_GROUP_60 );
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input BCLK,PHASE_0;
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input BCLK,PHASE_0;
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input [13:0] OPREG;
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input [18:0] OPREG;
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input [3:0] PHASE; // nur die 4 LSBs
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input [3:0] PHASE; // nur die 4 LSBs
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// Source 1 & 2 Inputs
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// Source 1 & 2 Inputs
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input [6:0] SRC_1,SRC_2,REGA1,REGA2,IRRW1,IRRW2;
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input [6:0] SRC_1,SRC_2,REGA1,REGA2,IRRW1,IRRW2;
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input [18:0] ADRD1,ADRD2,EXR12,EXR22;
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input [18:0] ADRD1,ADRD2,EXR12,EXR22;
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input [3:0] PHRD1,PHRD2;
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input [3:0] PHRD1,PHRD2;
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reg [7:0] phsrc1,phsrc2;
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reg [7:0] phsrc1,phsrc2;
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reg [5:0] chkreg;
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reg [5:0] chkreg;
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reg [1:0] bwdreg;
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reg [1:0] bwdreg;
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reg tbit_flag,size_dw;
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reg tbit_flag,size_dw;
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reg inss_flag;
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reg inss_flag;
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reg ext_tos;
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wire [18:0] exoffset,re_wr;
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wire [18:0] exoffset,re_wr,rexwr;
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wire [10:0] op_kust,op_bwd;
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wire [10:0] op_kust,op_bwd;
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wire [7:0] phchk;
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wire [7:0] phchk;
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wire [4:0] op_reg;
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wire [4:0] op_reg;
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wire [6:0] src_1l,src_2l;
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wire [6:0] src_1l,src_2l;
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wire [5:0] dest_2;
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wire [5:0] dest_2;
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parameter temp_h = 6'h3D; // Second last place for 8B TEMP Register
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parameter temp_h = 6'h3D; // Second last place for 8B TEMP Register
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parameter temp_1 = 6'h3E;
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parameter temp_1 = 6'h3E;
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parameter rtmpl = 7'h3C;
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parameter rtmpl = 7'h3C;
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parameter rtmph = 7'h3D;
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parameter rtmph = 7'h3D;
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parameter rtmp1 = 7'h3E;
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parameter rtmp1 = 7'h3E;
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parameter op_mov = {3'bxxx,8'h45};
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parameter op_mov = {3'bx1x,8'h45};
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parameter op_adr = {3'bxxx,8'h49};
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parameter op_adr = {3'bx1x,8'h49};
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parameter op_addl = {3'b0xx,8'hB0};
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parameter op_addl = {3'b01x,8'hB0};
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parameter op_addf = {3'b1xx,8'hB0};
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parameter op_addf = {3'b11x,8'hB0};
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parameter op_mull = {3'b0xx,8'hBC};
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parameter op_mull = {3'b01x,8'hBC};
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parameter op_mulf = {3'b1xx,8'hBC};
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parameter op_mulf = {3'b11x,8'hBC};
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parameter op_truf = {3'b101,8'h9A}; // TRUNCFW for SCALBF
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parameter op_truf = {3'b101,8'h9A}; // TRUNCFW for SCALBF
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parameter op_trul = {3'b001,8'h9A}; // TRUNCLW for SCALBL
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parameter op_trul = {3'b001,8'h9A}; // TRUNCLW for SCALBL
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parameter op_stpr = {3'b1xx,8'h54}; // Special-Op for String opcodes
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parameter op_stpr = {3'b11x,8'h54}; // Special-Op for String opcodes
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parameter op_lsh = {3'b011,8'h65}; // EXT : shift to right : DOUBLE !
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parameter op_lsh = {3'b011,8'h65}; // EXT : shift to right : DOUBLE !
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parameter op_msk = {3'b011,8'h80}; // reuse of EXT Opcode at INS !
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parameter op_msk = {3'b011,8'h80}; // reuse of EXT Opcode at INS !
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parameter op_mul = {3'b011,8'h78}; // INDEX
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parameter op_mul = {3'b011,8'h78}; // INDEX
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parameter op_rwv = {3'bxxx,8'hE0}; // RDVAL+WRVAL
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parameter op_rwv = {3'bx1x,8'hE0}; // RDVAL+WRVAL
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always @(OPREG) // whether the Opcode is valid is decided in DECODER !
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always @(OPREG) // whether the Opcode is valid is decided in DECODER !
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casex (OPREG) // [13:0]
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casex (OPREG[13:0])
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14'bxx_xxxx_1111_1110 : op_code = {2'b01,OPREG[11:10],OPREG[8]}; // DOT/POLY/SCALB
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14'bxx_xxxx_1111_1110 : op_code = {2'b01,OPREG[11:10],OPREG[8]}; // DOT/POLY/SCALB
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14'b00_0xxx_0000_1110 : op_code = 5'b1_0000; // MOVS/CMPS
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14'b00_0xxx_0000_1110 : op_code = 5'b1_0000; // MOVS/CMPS
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14'b00_11xx_0000_1110 : op_code = 5'b1_0000; // SKPS
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14'b00_11xx_0000_1110 : op_code = 5'b1_0000; // SKPS
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14'b00_0xxx_1100_1110 : op_code = 5'b1_0001; // MOVM/CMPM
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14'b00_0xxx_1100_1110 : op_code = 5'b1_0001; // MOVM/CMPM
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14'bxx_xx10_0111_11xx : op_code = 5'b1_0010; // JUMP/JSR
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14'bxx_xx10_0111_11xx : op_code = 5'b1_0010; // JUMP/JSR
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endcase
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endcase
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assign get8b_d = (PHRD2 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 58
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assign get8b_d = (PHRD2 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 58
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assign src_1l = {SRC_1[6:1],1'b0};
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assign src_1l = {SRC_1[6:1],1'b0};
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assign src_2l = {SRC_2[6:1],1'b0};
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assign src_2l = {SRC_2[6:1],~SRC_2[0]}; // needed only for DEI/MEI
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assign dest_2 = SRC_2[5:0];
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assign dest_2 = SRC_2[5:0];
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assign phchk = {7'b0101_010,size_dw}; // Phase 54 or 55
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assign phchk = {7'b0101_010,size_dw}; // Phase 54 or 55
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assign op_kust = {1'bx,OPERA[9:8],8'h7A}; // Special-Opcode for MOVM/CMPM
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assign op_kust = {1'bx,OPERA[9:8],8'h7A}; // Special-Opcode for MOVM/CMPM
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assign op_bwd = {1'bx,OPERA[9:8],8'h45}; // for CASE and Bit opcodes
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assign op_bwd = {1'bx,OPERA[9:8],8'h45}; // for CASE and Bit opcodes
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assign re_wr = {EXR22[18:17],4'b0101,4'h0, 9'h003}; // REUSE Address : Write of rmw , top 2 Bits contain size
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assign re_wr = {EXR22[18:17],4'b0101,4'h0, 9'h003}; // REUSE Address : Write of rmw , top 2 Bits contain size
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always @(posedge BCLK) if (PHASE_0) ext_tos <= (OPREG[18:14] == 5'h17); // if TOS
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assign rexwr = {EXR22[18:17],4'b0101,4'h0, ext_tos, 8'h03}; // REUSE Addresse : Write von rmw , only for EXT and EXTS !
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always @(posedge BCLK) tbit_flag <= ~OPERA[1]; // due to Timing ...
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always @(posedge BCLK) tbit_flag <= ~OPERA[1]; // due to Timing ...
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always @(posedge BCLK) size_dw <= OPERA[9];
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always @(posedge BCLK) size_dw <= OPERA[9];
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always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]}; // for CHECK
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always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]}; // for CHECK
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assign rd_reg = (PHASE_0) ? {4'b0,OPREG[13:11]} : {1'b0,chkreg}; // for read operation at EXT/INS
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assign rd_reg = (PHASE_0) ? {4'b0,OPREG[13:11]} : {1'b0,chkreg}; // for read operation at EXT/INS
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{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here Adr(DEST) => EA
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{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here Adr(DEST) => EA
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: { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immediate read
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: { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immediate read
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state_55 = dont_care;
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state_55 = dont_care;
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state_58 = { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immediate read
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state_58 = { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immediate read
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state_59 = ACCA[1] ? // _..M.
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state_59 = ACCA[1] ? // _..M.
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{ re_wr, 8'h27, imme, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
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{ rexwr, 8'h27, imme, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
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: { addr_nop,8'h00, imme, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
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: { addr_nop,8'h00, imme, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
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state_5A = dont_care;
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state_5A = dont_care;
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end
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end
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5'b1_1010 : // EXT : BASE Operand => TEMP, calculate address of Destination
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5'b1_1010 : // EXT : BASE Operand => TEMP, calculate address of Destination
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begin
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begin
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: { addr_nop,8'h59, rd_reg,(ACCA[3] ? imme : rtmph),
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: { addr_nop,8'h59, rd_reg,(ACCA[3] ? imme : rtmph),
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1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
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1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
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state_55 = { exoffset,8'h54, rd_reg,src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h1 }; // Read Source, EA reuse
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state_55 = { exoffset,8'h54, rd_reg,src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h1 }; // Read Source, EA reuse
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state_58 = { addr_nop,8'h59, rd_reg,rtmph, 1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
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state_58 = { addr_nop,8'h59, rd_reg,rtmph, 1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
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state_59 = ACCA[1] ? // _..M.
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state_59 = ACCA[1] ? // _..M.
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{ re_wr, 8'h27, src_x, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
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{ rexwr, 8'h27, src_x, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
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: { addr_nop,8'h00, src_x, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
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: { addr_nop,8'h00, src_x, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
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state_5A = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }; // special case Mem-Mem
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state_5A = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }; // special case Mem-Mem
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end
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end
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5'b1_1011 : // INS/INSS : BASE Operand => TEMP, SRC2 read as Double ! RMW not tested (Phase x'6A) but uncritical
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5'b1_1011 : // INS/INSS : BASE Operand => TEMP, SRC2 read as Double ! RMW not tested (Phase x'6A) but uncritical
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begin
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begin
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