| Line 2... |
Line 2... |
//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: STEUER_MISC.v
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// Filename: STEUER_MISC.v
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// Version: 1.1 bug fix
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// Version: 2.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 21 January 2016
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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| Line 210... |
Line 210... |
reg [31:0] pc_adduse;
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reg [31:0] pc_adduse;
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reg [31:0] pc_ic_reg;
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reg [31:0] pc_ic_reg;
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reg [31:0] fpu_trap_pc;
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reg [31:0] fpu_trap_pc;
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reg IC_USER;
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reg IC_USER;
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|
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wire [31:0] branch,pc_jump,next_pc,pc_icache_i;
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wire [31:0] branch,pc_jump,pc_icache_i;
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|
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assign PC_SAVE = pc_adduse + {29'h0,USED};
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assign PC_SAVE = pc_adduse + {29'h0,USED};
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assign branch = PC_ARCHI + DISP;
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assign branch = PC_ARCHI + DISP;
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|
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assign pc_jump = LOAD_PC ? PC_NEW : branch;
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assign pc_jump = LOAD_PC ? PC_NEW : branch;
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assign next_pc = NEW ? pc_jump : PC_SAVE; // Only at NEW is the DISP correct !
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|
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) pc_adduse <= 32'h0;
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if (!BRESET) pc_adduse <= 32'h0;
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else
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else
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pc_adduse <= next_pc;
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pc_adduse <= NEW ? pc_jump : PC_SAVE; // Only at NEW is the DISP correct !
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|
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// The Architectur - PC : Address mode "Programm Memory"-relativ
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// The Architectur - PC : Address mode "Programm Memory"-relativ
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// no BRESET because NEXT_PCA is immediately valid
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// no BRESET because NEXT_PCA is immediately valid
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (FPU_TRAP) PC_ARCHI <= fpu_trap_pc; // go back !
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if (FPU_TRAP) PC_ARCHI <= fpu_trap_pc; // go back !
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| Line 273... |
Line 271... |
output VALID;
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output VALID;
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reg [7:1] filter;
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reg [7:1] filter;
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wire [7:0] mdat_0;
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wire [7:0] mdat_0;
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wire [3:0] mdat_1;
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wire [3:0] mdat_1;
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wire [1:0] mdat_2;
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always @(IPOS or DIN)
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always @(IPOS or DIN)
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case (IPOS)
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case (IPOS)
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3'd0 : filter = DIN[7:1];
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3'd0 : filter = DIN[7:1];
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3'd1 : filter = {DIN[7:2],1'b0};
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3'd1 : filter = {DIN[7:2],1'b0};
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| Line 291... |
Line 288... |
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assign mdat_0 = INIT ? DIN : {filter,1'b0};
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assign mdat_0 = INIT ? DIN : {filter,1'b0};
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assign OPOS[2] = (mdat_0[3:0] == 4'h0);
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assign OPOS[2] = (mdat_0[3:0] == 4'h0);
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assign mdat_1 = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];
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assign mdat_1 = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];
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assign OPOS[1] = (mdat_1[1:0] == 2'b00);
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assign OPOS[1] = (mdat_1[1:0] == 2'b00);
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assign mdat_2 = OPOS[1] ? mdat_1[3:2] : mdat_1[1:0];
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assign OPOS[0] = ~((mdat_1[2:1] == 2'b10) | mdat_1[0]);
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assign OPOS[0] = ~mdat_2[0];
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assign VALID = (mdat_1 != 4'b0000);
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assign VALID = (mdat_2 != 2'b00);
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|
|
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endmodule
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endmodule
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|
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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| Line 495... |
Line 491... |
parameter op_adr = {3'bx1x,8'h49};
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parameter op_adr = {3'bx1x,8'h49};
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parameter op_addl = {3'b01x,8'hB0};
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parameter op_addl = {3'b01x,8'hB0};
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parameter op_addf = {3'b11x,8'hB0};
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parameter op_addf = {3'b11x,8'hB0};
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parameter op_mull = {3'b01x,8'hBC};
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parameter op_mull = {3'b01x,8'hBC};
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parameter op_mulf = {3'b11x,8'hBC};
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parameter op_mulf = {3'b11x,8'hBC};
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parameter op_truf = {3'b101,8'h9A}; // TRUNCFW for SCALBF
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parameter op_trul = {3'b001,8'h9A}; // TRUNCLW for SCALBL
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parameter op_stpr = {3'b11x,8'h54}; // Special-Op for String opcodes
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parameter op_stpr = {3'b11x,8'h54}; // Special-Op for String opcodes
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parameter op_lsh = {3'b011,8'h65}; // EXT : shift to right : DOUBLE !
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parameter op_lsh = {3'b011,8'h65}; // EXT : shift to right : DOUBLE !
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parameter op_msk = {3'b011,8'h80}; // reuse of EXT Opcode at INS !
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parameter op_msk = {3'b011,8'h80}; // reuse of EXT Opcode at INS !
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parameter op_mul = {3'b011,8'h78}; // INDEX
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parameter op_mul = {3'b011,8'h78}; // INDEX
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parameter op_rwv = {3'bx1x,8'hE0}; // RDVAL+WRVAL
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parameter op_rwv = {3'bx1x,8'hE0}; // RDVAL+WRVAL
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|
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always @(OPREG) // whether the Opcode is valid is decided in DECODER !
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always @(OPREG) // whether the Opcode is valid is decided in DECODER !
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casex (OPREG[13:0])
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casex (OPREG[13:0])
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14'bxx_xxxx_1111_1110 : op_code = {2'b01,OPREG[11:10],OPREG[8]}; // DOT/POLY/SCALB
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14'bxx_xxxx_1111_1110 : op_code = {3'b011,OPREG[10],OPREG[8]}; // DOT/POLY
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14'b00_0xxx_0000_1110 : op_code = 5'b1_0000; // MOVS/CMPS
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14'b00_0xxx_0000_1110 : op_code = 5'b1_0000; // MOVS/CMPS
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14'b00_11xx_0000_1110 : op_code = 5'b1_0000; // SKPS
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14'b00_11xx_0000_1110 : op_code = 5'b1_0000; // SKPS
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14'b00_0xxx_1100_1110 : op_code = 5'b1_0001; // MOVM/CMPM
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14'b00_0xxx_1100_1110 : op_code = 5'b1_0001; // MOVM/CMPM
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14'bxx_xx10_0111_11xx : op_code = 5'b1_0010; // JUMP/JSR
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14'bxx_xx10_0111_11xx : op_code = 5'b1_0010; // JUMP/JSR
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14'bxx_x111_0111_11xx : op_code = 5'b1_0011; // CASE
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14'bxx_x111_0111_11xx : op_code = 5'b1_0011; // CASE
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| Line 552... |
Line 546... |
endcase
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endcase
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|
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assign get8b_d = (PHRD2 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 58
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assign get8b_d = (PHRD2 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 58
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|
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assign src_1l = {SRC_1[6:1],1'b0};
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assign src_1l = {SRC_1[6:1],1'b0};
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assign src_2l = {SRC_2[6:1],~SRC_2[0]}; // needed only for DEI/MEI
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assign src_2l = {SRC_2[6:1],~SRC_2[0]}; // used only for DEI and MEI
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assign dest_2 = SRC_2[5:0];
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assign dest_2 = SRC_2[5:0];
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|
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assign phchk = {7'b0101_010,size_dw}; // Phase 54 or 55
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assign phchk = {7'b0101_010,size_dw}; // Phase 54 or 55
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|
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assign op_kust = {1'bx,OPERA[9:8],8'h7A}; // Special-Opcode for MOVM/CMPM
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assign op_kust = {1'bx,OPERA[9:8],8'h7A}; // Special-Opcode for MOVM/CMPM
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assign op_bwd = {1'bx,OPERA[9:8],8'h45}; // for CASE and Bit opcodes
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assign op_bwd = {1'bx,OPERA[9:8],8'h45}; // for CASE and Bit opcodes
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assign re_wr = {EXR22[18:17],4'b0101,4'h0, 9'h003}; // REUSE Address : Write of rmw , top 2 Bits contain size
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assign re_wr = {EXR22[18:17],4'b0101,4'h0, 9'h003}; // REUSE Address : Write of rmw , top 2 Bits contain size
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always @(posedge BCLK) if (PHASE_0) ext_tos <= (OPREG[18:14] == 5'h17); // if TOS
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always @(posedge BCLK) if (PHASE_0) ext_tos <= (OPREG[18:14] == 5'h17); // TOS Address mode
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assign rexwr = {EXR22[18:17],4'b0101,4'h0, ext_tos, 8'h03}; // REUSE Addresse : Write von rmw , only for EXT and EXTS !
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assign rexwr = {EXR22[18:17],4'b0101,4'h0, ext_tos, 8'h03}; // REUSE Address : Write of rmw , only for EXT and EXTS
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always @(posedge BCLK) tbit_flag <= ~OPERA[1]; // due to Timing ...
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always @(posedge BCLK) tbit_flag <= ~OPERA[1]; // due to Timing ...
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always @(posedge BCLK) size_dw <= OPERA[9];
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always @(posedge BCLK) size_dw <= OPERA[9];
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always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]}; // for CHECK
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always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]}; // for CHECK
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| Line 792... |
Line 786... |
state_55 = dont_care;
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state_55 = dont_care;
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state_58 = dont_care;
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state_58 = dont_care;
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state_59 = dont_care;
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state_59 = dont_care;
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state_5A = dont_care;
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state_5A = dont_care;
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end
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end
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5'b01_000 : // SCALBL : RMW critical !
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begin
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STATE_0 = ACCA[3] ? // _M...
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{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
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: { addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 };
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state_50 = ACCA[3] ? // _M...
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{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
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: { addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 };
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state_53 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,get8b_s };
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state_54 = ACCA[1] ?
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{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_trul, 2'b00,2'b00,NXRW2 }
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: { addr_nop,8'h5A, src_x, src_x, 1'b0,temp_h,op_trul, 2'b00,2'b00,4'h0 };
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state_55 = { addr_nop,8'h54, rtmph, imme, 1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 }; // 2. half of external SRC1
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state_58 = { addr_nop,8'h59, rtmph, imme, 1'b0,dest_2,OPERA, 2'b01,2'b00,4'h0 };
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state_59 = { addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),
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~ACCA[1],dest_2,OPERA, 2'b10,2'b00,4'h0 };
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state_5A = { addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_2,OPERA, 2'b01,2'b00,4'h0 }; // empty cycle for TRUNC => TEMP !
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|
end
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5'b01_001 : // SCALBF : RMW critical !
|
|
begin
|
|
STATE_0 = ACCA[3] ? // _M...
|
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{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
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: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0 };
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state_50 = ACCA[3] ? // _M...
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{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
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: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0 };
|
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state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0 };
|
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state_54 = ACCA[1] ?
|
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }
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: { addr_nop,8'h1F, rtmph, SRC_2, 1'b1,dest_2,OPERA, 2'b11,2'b00,4'h0 };
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state_55 = dont_care;
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state_58 = { addr_nop,8'h1F, rtmph, imme, 1'b0,dest_x,OPERA, 2'b11,2'b00,4'h0 };
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state_59 = dont_care;
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state_5A = dont_care;
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end
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|
5'b01_100 : // POLYL
|
5'b01_100 : // POLYL
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
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{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
|
: { addr_nop,8'h54, SRC_1, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
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| Line 848... |
Line 807... |
end
|
end
|
5'b01_101 : // POLYF
|
5'b01_101 : // POLYF
|
begin
|
begin
|
STATE_0 = ACCA[3] ? // _M...
|
STATE_0 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
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: { addr_nop,8'h54, SRC_1, F0, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h55, SRC_1, F0, 1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0 };
|
state_50 = ACCA[3] ? // _M...
|
state_50 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { addr_nop,8'h54, SRC_1, F0, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
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: { addr_nop,8'h55, SRC_1, F0, 1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0 };
|
state_53 = { addr_nop,8'h54, imme, F0, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
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state_53 = { addr_nop,8'h55, imme, F0, 1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0 };
|
state_54 = ACCA[1] ?
|
state_54 = ACCA[1] ?
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }
|
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }
|
: { addr_nop,8'h00, rtmph, SRC_2, 1'b1,w_F0 ,op_addf, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h6E, rtmph, SRC_2, 1'b0,dest_x,op_addf, 2'b11,2'b00,4'h0 };
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state_55 = dont_care;
|
state_55 = { addr_nop,8'h54, src_x, src_x, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
|
state_58 = { addr_nop,8'h00, rtmph, imme, 1'b1,w_F0 ,op_addf, 2'b00,2'b00,4'h0 };
|
state_58 = { addr_nop,8'h6E, rtmph, imme, 1'b0,dest_x,op_addf, 2'b11,2'b00,4'h0 };
|
state_59 = dont_care;
|
state_59 = dont_care;
|
state_5A = dont_care;
|
state_5A = dont_care;
|
end
|
end
|
5'b01_110 : // DOTL
|
5'b01_110 : // DOTL
|
begin
|
begin
|
| Line 885... |
Line 844... |
state_5A = { addr_nop,8'h61, rtmph, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
|
state_5A = { addr_nop,8'h61, rtmph, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
|
end
|
end
|
5'b01_111 : // DOTF
|
5'b01_111 : // DOTF
|
begin
|
begin
|
STATE_0 = (~ACCA[3] & ~ACCA[1]) ? // _R.R.
|
STATE_0 = (~ACCA[3] & ~ACCA[1]) ? // _R.R.
|
{ addr_nop,8'h63, SRC_1 ,SRC_2 ,1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 } // opera = MULF
|
{ addr_nop,8'h63, SRC_1 ,SRC_2 ,1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0 } // opera = MULF
|
: ( ACCA[3] ? // _M...
|
: ( ACCA[3] ? // _M...
|
{ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: {ADRD2, phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } );
|
: {ADRD2, phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } );
|
state_50 = ACCA[3] ? // _M...
|
state_50 = ACCA[3] ? // _M...
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
|
: { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
|
: { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
|
state_53 = ACCA[1] ? // _..M.
|
state_53 = ACCA[1] ? // _..M.
|
{ addr_nop,8'h55, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }
|
{ addr_nop,8'h55, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }
|
: { addr_nop,8'h63, imme, SRC_2 ,1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
|
: { addr_nop,8'h63, imme, SRC_2 ,1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0 };
|
state_54 = dont_care;
|
state_54 = dont_care;
|
state_55 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
|
state_55 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
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state_58 = { addr_nop,8'h63, (ACCA[3] ? rtmph : SRC_1), //_M...
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state_58 = { addr_nop,8'h63, (ACCA[3] ? rtmph : SRC_1), //_M...
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imme, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
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imme, 1'b0,dest_x,op_mulf, 2'b11,2'b00,4'h0 };
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state_59 = dont_care;
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state_59 = dont_care;
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state_5A = dont_care;
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state_5A = dont_care;
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end
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end
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default
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default
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begin
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begin
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| Line 940... |
Line 899... |
always @(*)
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always @(*)
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casex (PHASE)
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casex (PHASE)
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4'h0 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b1,chkreg,op_adr, 2'b00,2'b00,4'h0 }; // for INDEX
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4'h0 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b1,chkreg,op_adr, 2'b00,2'b00,4'h0 }; // for INDEX
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4'h1 : STATE_GROUP_60 = { addr_nop,8'h62, rtmpl, F0, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0 }; // for DOTL
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4'h1 : STATE_GROUP_60 = { addr_nop,8'h62, rtmpl, F0, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0 }; // for DOTL
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4'h2 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b0,w_F0_h,op_addl, 2'b00,2'b00,4'h0 }; // for DOTL & POLYL !
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4'h2 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b0,w_F0_h,op_addl, 2'b00,2'b00,4'h0 }; // for DOTL & POLYL !
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4'h3 : STATE_GROUP_60 = { addr_nop,8'h00, rtmph, F0, 1'b1,w_F0, op_addf, 2'b00,2'b00,4'h0 }; // for DOTF
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4'h3 : STATE_GROUP_60 = { addr_nop,8'h6F, src_x, src_x, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 }; // for DOTF
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4'hF : STATE_GROUP_60 = { addr_nop,8'h6E, rtmph, F0, 1'b0,dest_x,op_addf, 2'b11,2'b00,4'h0 };
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4'hE : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b1,w_F0, op_addf, 2'b00,2'b00,4'h0 }; // for DOTF & POLYF
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4'h4 : STATE_GROUP_60 = ACCA[1] ? // ..M.
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4'h4 : STATE_GROUP_60 = ACCA[1] ? // ..M.
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{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,temp_h,op_mull, 2'b00,2'b00,NXRW2 }
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{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,temp_h,op_mull, 2'b00,2'b00,NXRW2 }
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: { addr_nop,8'h59, SRC_2, rtmph, 1'b0,temp_h,op_addl, 2'b01,2'b00,4'h0 }; // for POLYL
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: { addr_nop,8'h59, SRC_2, rtmph, 1'b0,temp_h,op_addl, 2'b01,2'b00,4'h0 }; // for POLYL
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4'h5 : STATE_GROUP_60 = { addr_nop,8'h59, src_x, src_x, 1'b1,temp_l,op_kust, 2'b00,2'b00,4'h0 }; // for MOVM/CMPM
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4'h5 : STATE_GROUP_60 = { addr_nop,8'h59, src_x, src_x, 1'b1,temp_l,op_kust, 2'b00,2'b00,4'h0 }; // for MOVM/CMPM
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4'h6 : STATE_GROUP_60 = { addr_nop,8'h01, rtmph, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // for JUMP/JSR/CASE
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4'h6 : STATE_GROUP_60 = { addr_nop,8'h01, rtmph, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // for JUMP/JSR/CASE
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