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Line 34... |
//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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// 2. MAKE_STAT Generate Statistic Signals
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// 2. MAKE_STAT Generate Statistic Signals
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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|
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module IO_SWITCH ( BCLK, BRESET, I_IOA, D_IOA, I_IORD, D_IORD, D_IOWR, IO_READY, GENSTAT, D_IOBE, IL
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module IO_SWITCH ( BCLK, BRESET, I_IOA, D_IOA, I_IORD, D_IORD, D_IOWR, IO_READY, GENSTAT, D_IOBE, ILO_SIG, DCWACC,
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IO_A, IO_RD, IO_WR, IO_BE, I_IORDY, D_IORDY, STATUS, ILO );
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IO_A, IO_RD, IO_WR, IO_BE, I_IORDY, D_IORDY, STATUS, ILO );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input [31:0] I_IOA,D_IOA;
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input [31:0] I_IOA,D_IOA;
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input I_IORD;
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input I_IORD;
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Line 128... |
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assign ILO = ILO_SIG & ((D_IORD & sel_dp) | DCWACC[0] | ilo_flag | D_IOWR | DCWACC[1]);
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assign ILO = ILO_SIG & ((D_IORD & sel_dp) | DCWACC[0] | ilo_flag | D_IOWR | DCWACC[1]);
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endmodule
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endmodule
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. MAKE_STAT Generate Statistic Signals
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// 2. MAKE_STAT Generate Statistic Signals
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module MAKE_STAT ( BCLK, READ, DACC_OK, DC_ACC, DPTE_ACC, DC_MDONE, DRAM_WR, IC_READ, IACC_OK, DATA_
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module MAKE_STAT ( BCLK, READ, DACC_OK, DC_ACC, DPTE_ACC, DC_MDONE, DRAM_WR, IC_READ, IACC_OK, DATA_HOLD,
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IC_ACC, IPTE_ACC, IC_MDONE, KOLLISION, STATSIGS );
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IC_ACC, IPTE_ACC, IC_MDONE, KOLLISION, STATSIGS );
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input BCLK;
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input BCLK;
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input READ,DACC_OK;
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input READ,DACC_OK;
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input DC_ACC,DPTE_ACC,DC_MDONE;
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input DC_ACC,DPTE_ACC,DC_MDONE;
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