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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: TOP_MISC.v
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// Filename: TOP_MISC.v
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// Version: 2.0
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// Version: 3.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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// Date: 2 December 2018
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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// 2. MAKE_STAT Generate Statistic Signals
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// 2. MAKE_STAT Generate Statistic Signals
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//
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//
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assign IO_WR = sel_dp ? D_IOWR : 1'b0;
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assign IO_WR = sel_dp ? D_IOWR : 1'b0;
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assign IO_A = sel_dp ? D_IOA : I_IOA;
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assign IO_A = sel_dp ? D_IOA : I_IOA;
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assign IO_BE = sel_dp ? D_IOBE : 4'b1111; // Instruction read always 32 Bit
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assign IO_BE = sel_dp ? D_IOBE : 4'b1111; // Instruction read always 32 Bit
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assign D_IORDY = sel_dp & IO_READY;
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assign D_IORDY = sel_dp & IO_READY;
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assign I_IORDY = ~sel_dp & IO_READY;
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assign I_IORDY = ~sel_dp & IO_READY & I_IORD;
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assign interrupt = GENSTAT[1] | GENSTAT[0];
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assign interrupt = GENSTAT[1] | GENSTAT[0];
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always @(*)
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always @(*)
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casex ({sel_dp,daten,interrupt,I_IORD})
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casex ({sel_dp,daten,interrupt,I_IORD})
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