Line 98... |
Line 98... |
tri1 nWr;
|
tri1 nWr;
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tri1 [ 3:0] XA;
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tri1 [ 3:0] XA;
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tri1 [15:0] A;
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tri1 [15:0] A;
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tri1 [ 7:0] DB;
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tri1 [ 7:0] DB;
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|
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//tri1 nSel;
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//tri1 SCk;
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//tri1 MOSI;
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//reg MISO;
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|
|
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wire [4:0] LED;
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wire [4:0] LED;
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|
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// Define simulation variables
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// Define simulation variables
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|
|
reg Sim_nSO, Sim_nNMI, Sim_nIRQ;
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reg Sim_nSO, Sim_nNMI, Sim_nIRQ;
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reg [ 7:0] TestNum;
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reg [ 7:0] TestNum;
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reg [17:0] chkdad, chkadd;
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reg [17:0] chkdad, chkadd;
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|
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//integer i = 0;
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|
|
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integer cycle_cnt = 0;
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integer cycle_cnt = 0;
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integer instr_cnt = 0;
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integer instr_cnt = 0;
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|
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integer Loop_Start = 0;
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integer Loop_Start = 0;
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integer Hist_File = 0; // File handle for instruction histogram
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integer Hist_File = 0; // File handle for instruction histogram
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//integer SV_Output = 0; // File handle for State Vector Outputs
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reg [31:0] Hist [255:0]; // Instruction Histogram array
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reg [31:0] Hist [255:0]; // Instruction Histogram array
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reg [31:0] val; // Instruction Histogram variable
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reg [31:0] val; // Instruction Histogram variable
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reg [31:0] i, j; // loop counters
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reg [31:0] i, j; // loop counters
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//reg [((5*8) - 1):0] Op; // Processor Mode Mnemonics String
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//reg [((6*8) - 1):0] Opcode; // Opcode Mnemonics String
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//reg [((9*8) - 1):0] AddrMd; // Addressing Mode Mnemonics String
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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M65C02 #(
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M65C02 #(
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.pBootROM_File("M65C02_Tst5.txt")
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.pBootROM_File("Src/M65C02_Tst5.txt")
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) uut (
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) uut (
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.nRst(nRst),
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.nRst(nRst),
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.nRstO(nRstO),
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.nRstO(nRstO),
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.ClkIn(ClkIn),
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.ClkIn(ClkIn),
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.Phi1O(Phi1O),
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.Phi1O(Phi1O),
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.Phi2O(Phi2O),
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.Phi2O(Phi2O),
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.nSO(nSO),
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.nNMI(nNMI),
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.nNMI(nNMI),
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.nIRQ(nIRQ),
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.nIRQ(nIRQ),
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.nVP(nVP),
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.nVP(nVP),
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|
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.BE_In(BE_In),
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.BE_In(BE_In),
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.Sync(Sync),
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.Sync(Sync),
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.nML(nML),
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.nML(nML),
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|
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.nCE(nCE),
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.nCE(nCE),
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.RnW(RnW),
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.RnW(RnW),
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.nWr(nWr),
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.nOE(nOE),
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.nOE(nOE),
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.nWE(nWr),
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.Rdy(Rdy),
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.Rdy(Rdy),
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.XA(XA),
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.XA(XA),
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.A(A),
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.A(A),
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.DB(DB),
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.DB(DB),
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.nWP_In(1'b0),
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.nWP_In(1'b0),
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|
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.nWait(nWait),
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.nWait(nWait),
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|
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.LED(LED),
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.LED(LED)
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|
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.nSel(nSel),
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.SCk(SCk),
|
|
.MOSI(MOSI),
|
|
.MISO(MISO)
|
|
);
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|
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//// Instantiate Boot/Monitor ROM Module
|
// .LED(LED),
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//
|
//
|
//wire [7:0] ROM_DO;
|
// .nSel(nSel),
|
//reg ROM_WE;
|
// .SCk(SCk),
|
//
|
// .MOSI(MOSI),
|
//M65C02_RAM #(
|
// .MISO(MISO)
|
// .pAddrSize(pRAM_AddrWidth),
|
);
|
// .pDataSize(8),
|
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// .pFileName("M65C02_Tst3.txt")
|
|
// ) ROM (
|
|
// .Clk(~Phi2O),
|
|
//// .Ext(1'b1), // 4 cycle memory
|
|
//// .ZP(1'b0),
|
|
//// .Ext(1'b0), // 2 cycle memory
|
|
//// .ZP(1'b0),
|
|
// .Ext(1'b0), // 1 cycle memory
|
|
// .ZP(1'b1),
|
|
// .WE(ROM_WE),
|
|
// .AI(A[(pRAM_AddrWidth - 1):0]),
|
|
// .DI(DB),
|
|
// .DO(ROM_DO)
|
|
// );
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|
|
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// Instantiate RAM Module
|
// Instantiate RAM Module
|
|
|
wire [7:0] RAM_DO;
|
wire [7:0] RAM_DO;
|
reg RAM_WE;
|
reg RAM_WE;
|
|
|
M65C02_RAM #(
|
M65C02_RAM #(
|
.pAddrSize(pRAM_AddrWidth),
|
.pAddrSize(pRAM_AddrWidth),
|
.pDataSize(8),
|
.pDataSize(8),
|
.pFileName("65C02_FT.txt")
|
.pFileName("Src/65C02_FT.txt")
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) RAM (
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) RAM (
|
.Clk(~Phi2O),
|
.Clk(~Phi2O),
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// .Ext(1'b1), // 4 cycle memory
|
// .Ext(1'b1), // 4 cycle memory
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// .ZP(1'b0),
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// .ZP(1'b0),
|
// .Ext(1'b0), // 2 cycle memory
|
// .Ext(1'b0), // 2 cycle memory
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Line 226... |
Line 192... |
ClkIn = 1;
|
ClkIn = 1;
|
Sim_nSO = 0;
|
Sim_nSO = 0;
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Sim_nNMI = 0;
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Sim_nNMI = 0;
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Sim_nIRQ = 0;
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Sim_nIRQ = 0;
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BE_In = 1;
|
BE_In = 1;
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//Rdy = 1;
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//MISO = 1;
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TestNum = 0;
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TestNum = 0;
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chkdad = 0;
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chkdad = 0;
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chkadd = 0;
|
chkadd = 0;
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|
|
// Intialize Simulation Time Format
|
// Intialize Simulation Time Format
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Line 243... |
Line 207... |
for(cycle_cnt = 0; cycle_cnt < 256; cycle_cnt = cycle_cnt + 1)
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for(cycle_cnt = 0; cycle_cnt < 256; cycle_cnt = cycle_cnt + 1)
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Hist[cycle_cnt] = 0;
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Hist[cycle_cnt] = 0;
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cycle_cnt = 0;
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cycle_cnt = 0;
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|
|
Hist_File = $fopen("M65C02_Hist_File.txt", "w");
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Hist_File = $fopen("M65C02_Hist_File.txt", "w");
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// SV_Output = $fopen("M65C02_SV_Output.txt", "w");
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|
|
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// Wait 100 ns for global reset to finish
|
// Wait 100 ns for global reset to finish
|
|
|
#101 nRst = 1;
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#101 nRst = 1;
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|
|
// Add stimulus here
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|
|
|
// Start the Simulation Loop
|
// Start the Simulation Loop
|
|
|
wait(A == pSim_Loop);
|
wait(A == pSim_Loop);
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@(posedge Phi1O);
|
@(posedge Phi1O);
|
|
|
Line 274... |
Line 235... |
@(posedge Phi1O);
|
@(posedge Phi1O);
|
if(A == pSim_Loop) begin
|
if(A == pSim_Loop) begin
|
@(posedge Phi1O);
|
@(posedge Phi1O);
|
@(posedge Phi1O);
|
@(posedge Phi1O);
|
@(posedge Phi1O);
|
@(posedge Phi1O);
|
$display("End of Simulation - Looping to Start detected/n");
|
|
$display("\tSuccess - All enabled tests passed.\n");
|
$display("\n\tTest Loop Complete\n");
|
|
$display("\tEnd of Simulation-Looping to Start detected\n");
|
|
$display("\t\tSuccess - All enabled tests passed.\n");
|
|
|
|
$fclose(Hist_File);
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|
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
end
|
end
|
join
|
join
|
Line 315... |
Line 281... |
chkadd = ((A == 16'h354E) ? (chkadd + 1) : chkadd);
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chkadd = ((A == 16'h354E) ? (chkadd + 1) : chkadd);
|
end
|
end
|
|
|
// Connect ROM/RAM to M65C02 memory bus
|
// Connect ROM/RAM to M65C02 memory bus
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|
|
//always @(*) ROM_WE <= Phi2O & A[15] & ~nWr;
|
|
always @(*) RAM_WE <= Phi2O & ~A[15] & ~nWr;
|
always @(*) RAM_WE <= Phi2O & ~A[15] & ~nWr;
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|
|
//assign DB = ((~nOE) ? ((A[15]) ? ROM_DO : RAM_DO) : {8{1'bZ}});
|
|
assign DB = ((~nOE) ? RAM_DO : {8{1'bZ}});
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assign DB = ((~nOE) ? RAM_DO : {8{1'bZ}});
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|
|
// Generate Simulate nIRQ signal based on writes by test program to address
|
// Generate Simulate nIRQ signal based on writes by test program to address
|
// 0xFFF8 (assert nIRQ) or 0xFFF9 (deassert nIRQ)
|
// 0xFFF8 (assert nIRQ) or 0xFFF9 (deassert nIRQ)
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|
|
Line 345... |
Line 309... |
|
|
always @(posedge uut.ClkGen.Clk)
|
always @(posedge uut.ClkGen.Clk)
|
begin
|
begin
|
if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
|
if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
|
cycle_cnt = 0;
|
cycle_cnt = 0;
|
else if(Phi1O & uut.C4)
|
else if(Phi1O & uut.Rdy)
|
cycle_cnt = ((A == 16'h0400) ? 1 : (cycle_cnt + 1));
|
cycle_cnt = ((A == 16'h0400) ? 1 : (cycle_cnt + 1));
|
end
|
end
|
|
|
always @(posedge uut.ClkGen.Clk)
|
always @(posedge uut.ClkGen.Clk)
|
begin
|
begin
|
if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
|
if((uut.ClkGen.Rst | ~uut.ClkGen.nRst))
|
instr_cnt = 0;
|
instr_cnt = 0;
|
else if(Sync & Phi1O & uut.C4)
|
else if(Sync & Phi1O & uut.Rdy)
|
instr_cnt = ((A == 16'h0400) ? 1 : (instr_cnt + 1));
|
instr_cnt = ((A == 16'h0400) ? 1 : (instr_cnt + 1));
|
end
|
end
|
|
|
// Perform Instruction Histogramming for coverage puposes
|
// Perform Instruction Histogramming for coverage puposes
|
|
|
always @(posedge uut.ClkGen.Clk)
|
always @(posedge uut.ClkGen.Clk)
|
begin
|
begin
|
// $fstrobe(SV_Output, "%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
|
|
// IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);
|
|
|
|
if(~(uut.ClkGen.Rst | ~uut.ClkGen.nRst)) begin
|
if(~(uut.ClkGen.Rst | ~uut.ClkGen.nRst)) begin
|
if(Sync & Phi2O & uut.C3) begin
|
if(uut.Rdy & uut.uP.CE_IR) begin
|
if((A == 16'h0400)) begin
|
if((A == pSim_Loop)) begin
|
if((Loop_Start == 1)) begin
|
if((Loop_Start == 1)) begin
|
for(i = 0; i < 16; i = i + 1)
|
for(i = 0; i < 16; i = i + 1) begin // lower nibble
|
for(j = 0; j < 16; j = j + 1) begin
|
for(j = 0; j < 16; j = j + 1) begin // upper nibble
|
val = Hist[(j * 16) + i];
|
val = Hist[(j * 16) + i];
|
Hist[(j * 16) + i] = 0;
|
Hist[(j * 16) + i] = 0;
|
if((j == 0))
|
if((j == 0) || (j == 8))
|
$fwrite(Hist_File, "\n%h : %h", ((j * 16) + i), val);
|
$fwrite(Hist_File, "\n%h : %d", (j*16)+i, val);
|
else
|
else
|
$fwrite(Hist_File, " %h", val);
|
$fwrite(Hist_File, " %d", val);
|
|
end
|
end
|
end
|
$fclose(Hist_File);
|
|
// $fclose(SV_Output);
|
|
|
|
$display("\nTest Loop Complete\n");
|
|
|
|
// $stop;
|
|
end else begin
|
end else begin
|
Loop_Start = 1;
|
Loop_Start = 1;
|
end
|
end
|
end
|
end
|
val = Hist[DB];
|
val = Hist[uut.uP.DI];
|
Hist[DB] = val + 1;
|
Hist[uut.uP.DI] = val + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//// Test Monitor System Function
|
|
//
|
|
//always @(posedge Phi1O)
|
|
//begin
|
|
// $monitor("%b, %b, %b, %h, %b, %b, %h, %b, %b, %b, %h, %b, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h, %h",
|
|
// IRQ_Msk, Sim_Int, Int, Vector, Done, SC, Mode, RMW, IntSvc, Rdy, IO_Op, Ref_Ack, AO, DI, DO, A, X, Y, S, P, PC, IR, OP1, OP2);
|
|
//end
|
|
|
|
endmodule
|
endmodule
|
|
|
|
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No newline at end of file
|
No newline at end of file
|