| Line 49... |
Line 49... |
mem_basic_unit basic_mem5(.reset(reset),.clk(clk),.Dw_iba_i(Dw5_iba_i),.ram_do(mem_u_o5),.StartFrm(StartFrm5),.EndFrm(EndFrm5),.header_to_dcp(headers_o5),.start_length(start_length5),.transmit_done(transmit_done5),.adr_valid(adr_valid5));
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mem_basic_unit basic_mem5(.reset(reset),.clk(clk),.Dw_iba_i(Dw5_iba_i),.ram_do(mem_u_o5),.StartFrm(StartFrm5),.EndFrm(EndFrm5),.header_to_dcp(headers_o5),.start_length(start_length5),.transmit_done(transmit_done5),.adr_valid(adr_valid5));
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mem_basic_unit basic_mem6(.reset(reset),.clk(clk),.Dw_iba_i(Dw6_iba_i),.ram_do(mem_u_o6),.StartFrm(StartFrm6),.EndFrm(EndFrm6),.header_to_dcp(headers_o6),.start_length(start_length6),.transmit_done(transmit_done6),.adr_valid(adr_valid6));
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mem_basic_unit basic_mem6(.reset(reset),.clk(clk),.Dw_iba_i(Dw6_iba_i),.ram_do(mem_u_o6),.StartFrm(StartFrm6),.EndFrm(EndFrm6),.header_to_dcp(headers_o6),.start_length(start_length6),.transmit_done(transmit_done6),.adr_valid(adr_valid6));
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endmodule
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endmodule
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module Complete_on_write(reset , clk , Dw_iba_i,ram_oe,ram_we,Completed_ram_do,same_DW_read,complete_Ack);
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module Complete_on_write(reset , clk , Dw_iba_i,ram_oe,ram_we,Completed_ram_do,same_DW_read,addr_valid);
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input reset, clk, ram_oe, ram_we;
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input reset, clk, ram_oe, ram_we;
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input [31:0] Dw_iba_i;
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input [31:0] Dw_iba_i;
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output [31:0] Completed_ram_do;
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output [31:0] Completed_ram_do;
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output complete_Ack;
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input [2:0] same_DW_read;
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input [2:0] same_DW_read;
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input addr_valid;
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reg [31:0] Completed_ram_do ;
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reg [31:0] Completed_ram_do ;
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reg [31:0] delay_data_unit_1 , delay_data_unit_2;
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reg [31:0] delay_data_unit_1 , delay_data_unit_2;
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initial delay_data_unit_1 = 32'h0;
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initial begin
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initial delay_data_unit_2 = 32'h0;
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delay_data_unit_1 = 32'h0;
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delay_data_unit_2 = 32'h0;
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assign complete_Ack = 1;
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xor_data = 0;
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cnt_fsm = 0;
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// fsm replacement trial version
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clk_cnt = 0;
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end
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reg xor_data;
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reg xor_data;
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//this blk to solve the read mem with unvalid ram_addr
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (addr_valid == 1)
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begin
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delay_data_unit_1<=Dw_iba_i;
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delay_data_unit_1<=Dw_iba_i;
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delay_data_unit_2<=delay_data_unit_1;
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delay_data_unit_2<=delay_data_unit_1;
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xor_data <= |(delay_data_unit_1^Dw_iba_i);
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xor_data <= |(delay_data_unit_1^Dw_iba_i);
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end
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else
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begin
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delay_data_unit_1 = 0;
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delay_data_unit_2 = 0;
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end
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end
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//
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reg [7:0]clk_cnt;
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reg [1:0]cnt_fsm;
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always @(posedge clk)
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begin
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case (cnt_fsm)
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2'h0: begin
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if (xor_data ==1)
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begin
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cnt_fsm = 1;
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clk_cnt = 0;
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end
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end
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2'h1: begin
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clk_cnt = clk_cnt+1;
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if (xor_data == 1)
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begin
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clk_cnt = 0;
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end
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end
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endcase
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end
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end
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reg [3:0] fsm_cycle;
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reg [3:0] fsm_cycle;
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initial fsm_cycle =0 ;
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initial fsm_cycle =0 ;
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always @ (posedge clk)
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always @ (posedge clk)
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| Line 115... |
Line 145... |
input [31:0] Dw_iba_i;
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input [31:0] Dw_iba_i;
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input [15:0] start_length;
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input [15:0] start_length;
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input adr_valid; // from dpq - request to release that addr
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input adr_valid; // from dpq - request to release that addr
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output transmit_done; // tell DPQ transmission completed for last request
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output transmit_done; // tell DPQ transmission completed for last request
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output [31:0] ram_do,header_to_dcp;
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output [31:0] ram_do,header_to_dcp;
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wire ram_ce , complete_Ack;
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wire ram_ce ;
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reg ram_oe , tst_reg;
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reg ram_oe , tst_reg;
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reg ram_we, ram_we_pre,ram_oe_pre , headers_2_dcp_en , dmac_en;
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reg ram_we, ram_we_pre,ram_oe_pre , headers_2_dcp_en , dmac_en;
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reg [7:0] ram_addr ,w_ram_addr ;
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reg [7:0] ram_addr ,w_ram_addr ;
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reg [31:0] Dmac_header,Dmac_header1 , header_to_dcp;
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reg [31:0] Dmac_header,Dmac_header1 , header_to_dcp;
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wire [31:0] ram_do1 ;
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wire [31:0] ram_do1 ;
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reg [7:0] header_out_length , header_out_start_addr, input_length , counter_length ;
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reg [7:0] header_out_length , header_out_start_addr, input_length , counter_length ;
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reg [2:0] same_DW_read_cnt , same_DW_free_cnt ;
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reg [2:0] same_DW_read_cnt , same_DW_free_cnt ;
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reg [3:0] fsm_state, counter_modulu8_fsm;
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reg [3:0] fsm_state, counter_modulu8_fsm;
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reg transmit_done, increment_same_DW;
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reg transmit_done, increment_same_DW;
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reg read_arguments_valid, read_valid , div_2_clk,div_4_clk;
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reg read_arguments_valid,read_argumets_valid_delay_unit1,read_argumets_valid_delay_unit2, read_valid , div_2_clk,div_4_clk;
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reg ipg_out_mem; // this bit indicate when we can start read again from mem.
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reg ipg_out_mem; // this bit indicate when we can start read again from mem.
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assign ram_ce = 1;
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assign ram_ce = 1;
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// assign ram_do = Dw1_iba_i;
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// assign ram_do = Dw1_iba_i;
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initial begin
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initial begin
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ram_addr =0;
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ram_addr =0;
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| Line 156... |
Line 186... |
begin
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begin
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div_2_clk = clk^div_2_clk;
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div_2_clk = clk^div_2_clk;
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prev_input <= Dw_iba_i;
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prev_input <= Dw_iba_i;
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ram_we <= |(prev_input^Dw_iba_i); //ram_we pulse every word change
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ram_we <= |(prev_input^Dw_iba_i); //ram_we pulse every word change
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ram_oe <= (~|(prev_input^Dw_iba_i));
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ram_oe <= (~|(prev_input^Dw_iba_i)) & read_argumets_valid_delay_unit2;
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read_argumets_valid_delay_unit1 <= read_arguments_valid;
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read_argumets_valid_delay_unit2 <=read_argumets_valid_delay_unit1;
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end
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end
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always @(posedge StartFrm)
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always @(posedge StartFrm)
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begin
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begin
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headers_2_dcp_en = 0;
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headers_2_dcp_en = 0;
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| Line 176... |
Line 206... |
begin
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begin
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headers_2_dcp_en=1;
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headers_2_dcp_en=1;
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dmac_en=1;
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dmac_en=1;
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end
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end
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//complete mem output upon write to mem interupts
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//complete mem output upon write to mem interupts
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Complete_on_write complete_on_write1(.reset(reset),.clk(clk),.Dw_iba_i(ram_do1),.ram_oe(ram_oe),.ram_we(ram_we),.Completed_ram_do(ram_do),.complete_Ack(complete_Ack),.same_DW_read(same_DW_read_cnt));
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Complete_on_write complete_on_write1(.reset(reset),.clk(clk),.Dw_iba_i(ram_do1),.ram_oe(ram_oe),.ram_we(ram_we),.Completed_ram_do(ram_do),.same_DW_read(same_DW_read_cnt),.addr_valid(read_argumets_valid_delay_unit2));
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// | 32bit dmac | 16 bit dmac | 8 bit length| 8 bit start addr|
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// | 32bit dmac | 16 bit dmac | 8 bit length| 8 bit start addr|
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//Go into write interval
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//Go into write interval
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always @ (posedge ram_we) //write interval
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always @ (posedge ram_we) //write interval
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begin
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begin
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w_ram_addr = w_ram_addr +1; //need better management on free mem when can write?
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w_ram_addr = w_ram_addr +1; //need better management on free mem when can write?
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| Line 364... |
Line 394... |
mem1
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mem1
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(
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(
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.clk (~clk),
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.clk (~clk),
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.rst (reset),
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.rst (reset),
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.ce (ram_ce), // Chip enable input, active high
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.ce (ram_ce), // Chip enable input, active high
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.we ({ram_we & complete_Ack,ram_we & complete_Ack,ram_we & complete_Ack,ram_we & complete_Ack}), // Write enable input, active high
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.we ({ram_we ,ram_we ,ram_we,ram_we }), // Write enable input, active high
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.oe (ram_oe), // Output enable input, active high
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.oe (ram_oe), // Output enable input, active high
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.addr (ram_addr), // address bus inputs
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.addr (ram_addr), // address bus inputs
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.di (Dw_iba_i), // input data bus
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.di (Dw_iba_i), // input data bus
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.dato (ram_do1) // output data bus
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.dato (ram_do1) // output data bus
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`ifdef ETH_BIST
|
`ifdef ETH_BIST
|
