| Line 374... |
Line 374... |
input [31:0] Dword;
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input [31:0] Dword;
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input reset ,clk , TxStartFrm , TxEndFrm;
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input reset ,clk , TxStartFrm , TxEndFrm;
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output TxStartFrm_0 , TxEndFrm_1;
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output TxStartFrm_0 , TxEndFrm_1;
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// output TxStartFrm_ , TxEndFrm_;
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// output TxStartFrm_ , TxEndFrm_;
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reg clk_div2 ,clk_div4 ;
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reg clk_div2 ,clk_div4 ;
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reg [2:0] mod4;
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reg [1:0] mod4;
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reg [1:0] mod4_;
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reg [1:0] mod4_;
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reg [7:0] byte;
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reg [7:0] byte;
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reg TxStartFrm_ , TxEndFrm_ ,TxStartFrm_1,TxStartFrm_2, start_en , start_en_ ,end_en , start_signal_detect;
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reg TxStartFrm_ , TxEndFrm_ ,TxStartFrm_1,TxStartFrm_2, start_en , start_en_ ,end_en , start_signal_detect;
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reg [9:0] counter;
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reg [9:0] counter;
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reg [1:0] FSMState;
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wire TxStartFrm_0 , TxEndFrm_1;
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wire TxStartFrm_0 , TxEndFrm_1;
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initial begin
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initial begin
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FSMState = 0;
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mod4=0;
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mod4=0;
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mod4_=0;
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mod4_=0;
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counter =0;
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counter =0;
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clk_div2=0;
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clk_div2=0;
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byte=0;
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byte=0;
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| Line 400... |
Line 402... |
end
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end
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always @(posedge TxEndFrm )
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always @(posedge TxEndFrm )
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begin
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begin
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end_en<=1;
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end_en<=1;
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mod4 <=0 ;
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// mod4 <=0 ;
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end
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end
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always @(posedge TxStartFrm )
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always @(posedge TxStartFrm )
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begin
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begin
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mod4_ <= 0;
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mod4_ <= 0;
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mod4 <= 0;
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// mod4 <= 0;
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counter=0;
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counter=0;
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// start_en<=1; //push simultaneously
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// start_en<=1; //push simultaneously
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//clk_div2=1;
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//clk_div2=1;
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end
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end
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| Line 425... |
Line 427... |
assign TxEndFrm_1 = end_en & (mod4==5);
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assign TxEndFrm_1 = end_en & (mod4==5);
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always @ (posedge clk_div2)
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always @ (posedge clk_div2)
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begin
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begin
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TxEndFrm_<=(mod4==4)?(~clk_div2)&end_en:TxEndFrm;
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TxEndFrm_<=(mod4==4)?(~clk_div2)&end_en:TxEndFrm;
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end_en<= (mod4==5)?0:end_en;
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end_en<= (mod4==5)?0:end_en;
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mod4<=mod4+1;
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mod4_<=mod4_+1;
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mod4_<=mod4_+1;
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start_signal_detect = |Dword;
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start_signal_detect = |Dword;
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TxStartFrm_=start_signal_detect & clk_div2;
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TxStartFrm_=start_signal_detect & clk_div2;
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if (start_signal_detect & clk_div2)
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if (start_signal_detect & clk_div2)
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begin
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begin
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| Line 437... |
Line 439... |
end
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end
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if (counter >0)
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if (counter >0)
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begin
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begin
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TxStartFrm_ =0;
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TxStartFrm_ =0;
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end
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end
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case(mod4_)
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end
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always @(negedge clk_div2)
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begin
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case(mod4)
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2'h0: byte<= Dword[31:24] ;
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2'h0: byte<= Dword[31:24] ;
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2'h1: byte<= Dword[23:16] ;
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2'h1: byte<= Dword[23:16] ;
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2'h2: byte<= Dword[15:8] ;
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2'h2: byte<= Dword[15:8] ;
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2'h3: byte<= Dword[7:0] ;
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2'h3: byte<= Dword[7:0] ;
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endcase
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endcase
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end
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end
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always @ (posedge clk_div2)
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begin
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case (FSMState)
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2'b00: begin // this is non recieving frame state
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if (start_signal_detect == 0)
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begin
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//FSMState <= 2'b00;
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mod4 <= 0;
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end
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else if (start_signal_detect == 1)
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begin
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FSMState <= 2'b11;
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mod4 <= mod4+1;
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end
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end
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// 2'b01: begin
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// if (start_signal_detect == 1)
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// begin
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// FSMState <= 2'b11;
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// mod4 <= 0;
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// end
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// end
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2'b11: begin
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if (start_signal_detect == 1)
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begin
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//FSMState <= 2'b11;
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mod4 <= mod4 +1;
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end
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else if (start_signal_detect==0)
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begin
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FSMState<= 2'b00;
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end
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end
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endcase
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end
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endmodule
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endmodule
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module byte_to_Dword(reset,clk ,byte ,Dword , RxStartFrm_ ,RxEndFrm_);
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module byte_to_Dword(reset,clk ,byte ,Dword , RxStartFrm_ ,RxEndFrm_);
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input [9:0] byte;
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input [9:0] byte;
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