| Line 135... |
Line 135... |
);
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);
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input reset , clk;
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input reset , clk;
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input [3:0] pi1,pi2,pi3,pi4,pi5,pi6;
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input [3:0] pi1,pi2,pi3,pi4,pi5,pi6;
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output [3:0] po1, po2,po3, po4,po5, po6;
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output [3:0] po1, po2,po3, po4,po5, po6;
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output [31:0] Dw1o,Dw2o,Dw3o,Dw4o,Dw5o,Dw6o;// to IBA
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output [31:0] Dw1o,Dw2o,Dw3o,Dw4o,Dw5o,Dw6o;// to IBA
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input [31:0] Dw1i,Dw2i,Dw3i,Dw4i,Dw5i,Dw6i;// from IBA
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input [31:0] Dw1i,Dw2i,Dw3i,Dw4i,Dw5i,Dw6i;// from Xbar
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output plu2iba_start_pack_1 , plu2iba_start_pack_2,plu2iba_start_pack_3,plu2iba_start_pack_4,plu2iba_start_pack_5,plu2iba_start_pack_6;
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output plu2iba_start_pack_1 , plu2iba_start_pack_2,plu2iba_start_pack_3,plu2iba_start_pack_4,plu2iba_start_pack_5,plu2iba_start_pack_6;
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input iba2plu_start_pack_1 , iba2plu_start_pack_2,iba2plu_start_pack_3,iba2plu_start_pack_4,iba2plu_start_pack_5,iba2plu_start_pack_6;
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input iba2plu_start_pack_1 , iba2plu_start_pack_2,iba2plu_start_pack_3,iba2plu_start_pack_4,iba2plu_start_pack_5,iba2plu_start_pack_6;
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output plu2iba_end_pack_1 , plu2iba_end_pack_2,plu2iba_end_pack_3,plu2iba_end_pack_4,plu2iba_end_pack_5,plu2iba_end_pack_6;
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output plu2iba_end_pack_1 , plu2iba_end_pack_2,plu2iba_end_pack_3,plu2iba_end_pack_4,plu2iba_end_pack_5,plu2iba_end_pack_6;
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input iba2plu_end_pack_1 , iba2plu_end_pack_2,iba2plu_end_pack_3,iba2plu_end_pack_4,iba2plu_end_pack_5,iba2plu_end_pack_6;
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input iba2plu_end_pack_1 , iba2plu_end_pack_2,iba2plu_end_pack_3,iba2plu_end_pack_4,iba2plu_end_pack_5,iba2plu_end_pack_6;
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| Line 232... |
Line 232... |
transmit_done3,
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transmit_done3,
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transmit_done4,
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transmit_done4,
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transmit_done5,
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transmit_done5,
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transmit_done6;
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transmit_done6;
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assign Dw1_iba_o=Dw1_iba_i; //initial LB configuration
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assign Dw1_iba_o=mem_u_o1;
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assign Dw2_iba_o=Dw2_iba_i; //initial LB configuration
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assign Dw2_iba_o=mem_u_o2; //Dw2_iba_i for LB
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assign Dw3_iba_o=Dw3_iba_i; //initial LB configuration
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assign Dw3_iba_o=mem_u_o3;
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assign Dw4_iba_o=Dw4_iba_i; //initial LB configuration
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assign Dw4_iba_o=mem_u_o4;
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assign Dw5_iba_o=Dw5_iba_i; //initial LB configuration
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assign Dw5_iba_o=mem_u_o5;
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assign Dw6_iba_o=Dw6_iba_i; //initial LB configuration
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assign Dw6_iba_o=mem_u_o6;
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assign iba2plu_start_pack_1 = plu2iba_start_pack_1;
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assign iba2plu_start_pack_1 = 0;
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assign iba2plu_start_pack_2 = plu2iba_start_pack_2;
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assign iba2plu_start_pack_2 = 0;
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assign iba2plu_start_pack_3 = plu2iba_start_pack_3;
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assign iba2plu_start_pack_3 = plu2iba_start_pack_3;
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assign iba2plu_start_pack_4 = plu2iba_start_pack_4;
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assign iba2plu_start_pack_4 = plu2iba_start_pack_4;
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assign iba2plu_start_pack_5 = plu2iba_start_pack_5;
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assign iba2plu_start_pack_5 = plu2iba_start_pack_5;
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assign iba2plu_start_pack_6 = plu2iba_start_pack_6;
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assign iba2plu_start_pack_6 = plu2iba_start_pack_6;
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assign iba2plu_end_pack_1 = plu2iba_end_pack_1;
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assign iba2plu_end_pack_1 = 0;
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assign iba2plu_end_pack_2 = plu2iba_end_pack_2;
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assign iba2plu_end_pack_2 = 0;
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assign iba2plu_end_pack_3 = plu2iba_end_pack_3;
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assign iba2plu_end_pack_3 = plu2iba_end_pack_3;
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assign iba2plu_end_pack_4 = plu2iba_end_pack_4;
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assign iba2plu_end_pack_4 = plu2iba_end_pack_4;
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assign iba2plu_end_pack_5 = plu2iba_end_pack_5;
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assign iba2plu_end_pack_5 = plu2iba_end_pack_5;
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assign iba2plu_end_pack_6 = plu2iba_end_pack_6;
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assign iba2plu_end_pack_6 = plu2iba_end_pack_6;
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wire [31:0] mem_u_o1,mem_u_o2,mem_u_o3,mem_u_o4,mem_u_o5,mem_u_o6;
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wire [31:0] mem_u_o1,mem_u_o2,mem_u_o3,mem_u_o4,mem_u_o5,mem_u_o6;
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| Line 328... |
Line 328... |
output adr_valid1,adr_valid2,adr_valid3,adr_valid4,adr_valid5,adr_valid6;
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output adr_valid1,adr_valid2,adr_valid3,adr_valid4,adr_valid5,adr_valid6;
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//fifo Qps need to validate addr_valid in the end
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//fifo Qps need to validate addr_valid in the end
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Qp qp1(.reset(reset),.clk(clk),.transmit_done(transmit_done1),.Din(start_addr1),.start_adr(start_length1),.T_q(T_q1),.adr_valid(adr_valid1));
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Qp qp1(.reset(reset),.clk(clk),.transmit_done(transmit_done1),.Din(start_addr1),.start_adr(start_length1),.T_q(T_q1),.adr_valid(adr_valid1));
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Qp qp2(.reset(reset),.clk(clk),.transmit_done(transmit_done2),.Din(start_addr2),.start_adr(start_length2),.T_q(T_q2),.adr_valid(adr_valid2));
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Qp qp3(.reset(reset),.clk(clk),.transmit_done(transmit_done3),.Din(start_addr3),.start_adr(start_length3),.T_q(T_q3),.adr_valid(adr_valid3));
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Qp qp4(.reset(reset),.clk(clk),.transmit_done(transmit_done4),.Din(start_addr4),.start_adr(start_length4),.T_q(T_q4),.adr_valid(adr_valid4));
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Qp qp5(.reset(reset),.clk(clk),.transmit_done(transmit_done5),.Din(start_addr5),.start_adr(start_length5),.T_q(T_q5),.adr_valid(adr_valid5));
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Qp qp6(.reset(reset),.clk(clk),.transmit_done(transmit_done6),.Din(start_addr6),.start_adr(start_length6),.T_q(T_q6),.adr_valid(adr_valid6));
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endmodule
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endmodule
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module Xbar(reset,clk,T_q1,Data_i1,Data_o1,xbar2plu_start_pack_1,xbar2plu_end_pack_1, // iba2xbar_start_pack_1,iba2xbar_end_pack_1,
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module Xbar(reset,clk,T_q1,Data_i1,Data_o1,xbar2plu_start_pack_1,xbar2plu_end_pack_1, // iba2xbar_start_pack_1,iba2xbar_end_pack_1,
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