| Line 19... |
Line 19... |
`include "timescale.v"
|
`include "timescale.v"
|
`include "iba_modules.v"
|
`include "iba_modules.v"
|
`include "dcp_modules.v"
|
`include "dcp_modules.v"
|
`include "dpq_modules.v"
|
`include "dpq_modules.v"
|
`include "plu_moduls.v"
|
`include "plu_moduls.v"
|
`include "Xbar_modules.v"
|
//`include "Xbar_modules.v"
|
|
|
|
|
|
|
//llu (, detect new frame,check crc, s2p) ->
|
//llu (, detect new frame,check crc, s2p) ->
|
//parser check correctness , seperate from L2->
|
//parser check correctness , seperate from L2->
|
| Line 365... |
Line 365... |
xbar2plu_start_pack_6,xbar2plu_end_pack_6;
|
xbar2plu_start_pack_6,xbar2plu_end_pack_6;
|
reg [31:0] Data_o1,Data_o2,Data_o3,Data_o4,Data_o5,Data_o6;
|
reg [31:0] Data_o1,Data_o2,Data_o3,Data_o4,Data_o5,Data_o6;
|
|
|
//create module that create start/end packet signals detect by delay and xor
|
//create module that create start/end packet signals detect by delay and xor
|
// delimiter_add
|
// delimiter_add
|
Alignment_marker align1(.reset(reset),.clk(clk),.Data_o(Data_o1),.iba2xbar_start_pack(iba2xbar_start_pack),.iba2xbar_end_pack(iba2xbar_end_pack),.xbar2plu_start_pack(xbar2plu_start_pack),.xbar2plu_end_pack(xbar2plu_end_pack));
|
// Alignment_marker align1(.reset(reset),.clk(clk),.Data_o(Data_o1),.iba2xbar_start_pack(iba2xbar_start_pack),.iba2xbar_end_pack(iba2xbar_end_pack),.xbar2plu_start_pack(xbar2plu_start_pack),.xbar2plu_end_pack(xbar2plu_end_pack));
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
case (T_q1)
|
case (T_q1)
|
8'h01: Data_o1 = Data_i1;
|
8'h01: Data_o1 = Data_i1;
|
