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-- when each transmitter bit is 3.24 ms and the FPGA clock is 50 MHz
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-- when each transmitter bit is 3.24 ms and the FPGA clock is 50 MHz
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-- then:
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-- then:
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-- single is nominally 23200
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-- single is nominally 23200
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constant INTERVAL_MIN_SINGLE: integer := 10000;
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constant INTERVAL_MIN_SINGLE: integer := 34000;--10000
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constant INTERVAL_MAX_SINGLE: integer := 65000;
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constant INTERVAL_MAX_SINGLE: integer := 65000;
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-- double is nominally 43000-50000
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-- double is nominally 43000-50000
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constant INTERVAL_MIN_DOUBLE: integer := 90000;--80000
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constant INTERVAL_MIN_DOUBLE: integer := 80000;--90000
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constant INTERVAL_MAX_DOUBLE: integer := 120000;
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constant INTERVAL_MAX_DOUBLE: integer := 120000;
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constant INTERVAL_QUADRUPLE: integer := 650000;--350000
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constant INTERVAL_QUADRUPLE: integer := 650000;--350000
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end globals;
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end globals;
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