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[/] [manchesterwireless/] [branches/] [singledouble/] [globals.vhd] - Diff between revs 6 and 12

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Rev 6 Rev 12
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  -- when each transmitter bit is 3.24 ms and the FPGA clock is 50 MHz
  -- when each transmitter bit is 3.24 ms and the FPGA clock is 50 MHz
  -- then:
  -- then:
 
 
  -- single is nominally 23200
  -- single is nominally 23200
  constant INTERVAL_MIN_SINGLE: integer := 10000;
  constant INTERVAL_MIN_SINGLE: integer := 34000;--10000
  constant INTERVAL_MAX_SINGLE: integer := 65000;
  constant INTERVAL_MAX_SINGLE: integer := 65000;
 
 
  -- double is nominally 43000-50000
  -- double is nominally 43000-50000
  constant INTERVAL_MIN_DOUBLE: integer := 90000;--80000
  constant INTERVAL_MIN_DOUBLE: integer := 80000;--90000
  constant INTERVAL_MAX_DOUBLE: integer := 120000;
  constant INTERVAL_MAX_DOUBLE: integer := 120000;
 
 
  constant INTERVAL_QUADRUPLE: integer  := 650000;--350000
  constant INTERVAL_QUADRUPLE: integer  := 650000;--350000
end globals;
end globals;
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