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URL https://opencores.org/ocsvn/manchesterwireless/manchesterwireless/trunk

Subversion Repositories manchesterwireless

[/] [manchesterwireless/] [branches/] [singledouble/] [simTest.vhd] - Diff between revs 6 and 12

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Rev 6 Rev 12
Line 6... Line 6...
entity testSim is
entity testSim is
end testSim;
end testSim;
 
 
architecture Behavioral of testSim is
architecture Behavioral of testSim is
 
 
  component decodeManchester
  component manchesterWireless
  port (
  port (
    clk_i             : in  std_logic;
    clk_i             : in  std_logic;
    rst_i             : in  std_logic;
    rst_i             : in  std_logic;
    data_i            : in  std_logic;
    data_i            : in  std_logic;
    q_o               : out std_logic_vector(WORD_LENGTH-1 downto 0);
    q_o               : out std_logic_vector(WORD_LENGTH-1 downto 0);
Line 52... Line 52...
  character_o(7) <= '1'; -- turn off decimal point
  character_o(7) <= '1'; -- turn off decimal point
 
 
  reset_manchester <=  rst_i or soft_reset;
  reset_manchester <=  rst_i or soft_reset;
  ready_o <= ready_o_buff;
  ready_o <= ready_o_buff;
 
 
  inst_decodeManchester: decodeManchester
  inst_manchesterWireless: manchesterWireless
  port map(
  port map(
    clk_i   => clk_i,
    clk_i   => clk_i,
    rst_i   => reset_manchester,
    rst_i   => reset_manchester,
    data_i  => data_i,
    data_i  => data_i,
    q_o     => decode_output,
    q_o     => decode_output,

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