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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use work.globals.all;
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use work.globals.all;
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entity testSim is
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entity testSim is
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end testSim;
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end testSim;
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signal reset_manchester, soft_reset, ready_o_buff : std_logic;
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signal reset_manchester, soft_reset, ready_o_buff : std_logic;
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signal clk_i : std_logic;
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signal clk_i : std_logic;
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signal rst_i : std_logic := '1';
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signal rst_i : std_logic := '1';
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signal data_i : std_logic;
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--signal data_i : std_logic;
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signal ready_o : std_logic;
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signal ready_o : std_logic;
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signal character_o : std_logic_vector(0 to 7);
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signal character_o : std_logic_vector(0 to 7);
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signal anode_ctrl : std_logic_vector(3 downto 0);
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signal anode_ctrl : std_logic_vector(3 downto 0);
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signal button_o : std_logic_vector(1 downto 0);
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signal button_o : std_logic_vector(1 downto 0);
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signal parity_o : std_logic;
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signal parity_o : std_logic;
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constant half_period : time := 10 ns;
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constant half_period : time := 10 ns;
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constant period : time := 2*half_period;
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constant period : time := 2*half_period;
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constant mid_single : time := (INTERVAL_MIN_SINGLE+INTERVAL_MAX_SINGLE)/2*period;
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constant mid_single : time := (INTERVAL_MIN_SINGLE+INTERVAL_MAX_SINGLE)/2*period;
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constant WORD : std_logic_vector(28 downto 0) := "01100101100101010101010101010";
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constant WORD : std_logic_vector(28 downto 0) := "01100101100101010101010101010";
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----------Added by Thiag-------------
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file TEST_IP : TEXT open READ_MODE is "six.dat";
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signal data_i : std_ulogic;
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constant BIT_PERIOD : time := 100 us;
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-------------------------------------
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begin
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begin
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character_o(7) <= '1'; -- turn off decimal point
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character_o(7) <= '1'; -- turn off decimal point
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reset_manchester <= rst_i or soft_reset;
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reset_manchester <= rst_i or soft_reset;
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ready_o <= ready_o_buff;
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ready_o <= ready_o_buff;
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variable counter : integer range 0 to 1023;
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variable counter : integer range 0 to 1023;
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begin
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begin
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if rst_i = '1' then
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if rst_i = '1' then
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char_select <= 0;
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char_select <= 0;
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counter := 0;
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counter := 0;
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div_clk := '0';
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--div_clk := '0';
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soft_reset <= '0';
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soft_reset <= '0';
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elsif (clk_i'event and clk_i = '1') then
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elsif (clk_i'event and clk_i = '1') then
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-- register the output
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-- register the output
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if (ready_o_buff = '1') then
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if (ready_o_buff = '1') then
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ud_buff1_reg <= ud_buff1;
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ud_buff1_reg <= ud_buff1;
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anode_ctrl <= "0111" when 0,
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anode_ctrl <= "0111" when 0,
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"1011" when 1,
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"1011" when 1,
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"1101" when 2,
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"1101" when 2,
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"1110" when 3;
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"1110" when 3;
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--process
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--begin
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-- wait for 5*period;
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-- rst_i <= '0';
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-- -- begin transmission header
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-- data_i <= '1';
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-- wait for 5*MID_SINGLE;
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--
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-- data_i <= '0';
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-- wait for MID_SINGLE;
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-- -- end transmission header
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-- for i in WORD'left downto 0 loop
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-- data_i <= WORD(i);
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-- wait for MID_SINGLE;
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-- end loop;
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-- data_i <= '1';
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-- wait for MID_SINGLE;
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--
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-- rst_i <= '1';
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-- wait for 5*period;
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--end process;
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process
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process
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variable LINE_BUF : LINE;
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variable IP_BIT : BIT;
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begin
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begin
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wait for 5*period;
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wait for 5*period;
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rst_i <= '0';
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rst_i <= '0';
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-- begin transmission header
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while not ENDFILE (TEST_IP) loop
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data_i <= '1';
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READLINE (TEST_IP,LINE_BUF);
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wait for 5*MID_SINGLE;
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while (LINE_BUF'LENGTH /= 0) loop
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READ(LINE_BUF,IP_BIT);
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data_i <= '0';
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data_i <= TO_STDULOGIC(IP_BIT);
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wait for MID_SINGLE;
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wait for BIT_PERIOD;
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-- end transmission header
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for i in WORD'left downto 0 loop
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data_i <= WORD(i);
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wait for MID_SINGLE;
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end loop;
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end loop;
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end loop;
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data_i <= '1';
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assert (FALSE)
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wait for MID_SINGLE;
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report "End of Input Data"
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severity ERROR;
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rst_i <= '1';
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wait for 5*period;
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end process;
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end process;
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clock : process
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clock : process
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begin
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begin
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clk_i <= '1';
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clk_i <= '1';
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