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[/] [manchesterwireless/] [trunk/] [singleDouble/] [simTest.vhd] - Diff between revs 7 and 8

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Rev 7 Rev 8
Line 7... Line 7...
entity test_sim is
entity test_sim is
end test_sim;
end test_sim;
 
 
architecture Behavioral of test_sim is
architecture Behavioral of test_sim is
 
 
        COMPONENT singleDouble_original
 
        PORT(
 
    clk_i   :  in  std_logic;
 
    ce_i    :  in  std_logic;
 
    rst_i   :  in  std_logic;
 
    data_i  :  in  std_logic;
 
    q_o     :  out std_logic_vector(3 downto 0);
 
    ready_o :  out std_logic
 
                );
 
        END COMPONENT;
 
 
 
  COMPONENT singleDouble
  COMPONENT singleDouble
        PORT(
        PORT(
    clk_i   :  in  std_logic;
    clk_i   :  in  std_logic;
    ce_i    :  in  std_logic;
    ce_i    :  in  std_logic;
Line 32... Line 22...
        END COMPONENT;
        END COMPONENT;
 
 
  signal clk : std_logic := '0';
  signal clk : std_logic := '0';
  signal ce_i : std_logic := '0';
  signal ce_i : std_logic := '0';
  signal mdi : std_logic := '0';
  signal mdi : std_logic := '0';
  signal q_orig : std_logic_vector(3 downto 0);
 
  signal nd_orig : std_logic;
 
  signal q_modified : std_logic_vector(3 downto 0);
  signal q_modified : std_logic_vector(3 downto 0);
  signal nd_modified : std_logic;
  signal nd_modified : std_logic;
 
 
  constant period : time := 10 ns;
  constant period : time := 10 ns;
  constant md_period : time := period*16;
  constant md_period : time := period*16;
  signal reset : std_logic := '1';
  signal reset : std_logic := '1';
begin
begin
 
 
        Inst_orig: singleDouble_original PORT MAP(
 
    clk_i =>  clk,
 
    ce_i  =>  ce_i,
 
    rst_i  =>  reset,
 
    data_i   =>  mdi,
 
    q_o     =>  q_orig,
 
    ready_o    =>  nd_orig
 
        );
 
 
 
  Inst_modified: singleDouble PORT MAP(
  Inst_modified: singleDouble PORT MAP(
    clk_i =>  clk,
    clk_i =>  clk,
    ce_i  =>  ce_i,
    ce_i  =>  ce_i,
    rst_i  =>  reset,
    rst_i  =>  reset,
    data_i   =>  mdi,
    data_i   =>  mdi,

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