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https://opencores.org/ocsvn/manchesterwireless/manchesterwireless/trunk
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entity test_sim is
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entity test_sim is
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end test_sim;
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end test_sim;
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architecture Behavioral of test_sim is
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architecture Behavioral of test_sim is
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COMPONENT singleDouble_original
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PORT(
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clk_i : in std_logic;
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ce_i : in std_logic;
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rst_i : in std_logic;
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data_i : in std_logic;
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q_o : out std_logic_vector(3 downto 0);
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ready_o : out std_logic
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);
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END COMPONENT;
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COMPONENT singleDouble
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COMPONENT singleDouble
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PORT(
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PORT(
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clk_i : in std_logic;
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clk_i : in std_logic;
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ce_i : in std_logic;
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ce_i : in std_logic;
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END COMPONENT;
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END COMPONENT;
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal ce_i : std_logic := '0';
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signal ce_i : std_logic := '0';
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signal mdi : std_logic := '0';
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signal mdi : std_logic := '0';
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signal q_orig : std_logic_vector(3 downto 0);
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signal nd_orig : std_logic;
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signal q_modified : std_logic_vector(3 downto 0);
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signal q_modified : std_logic_vector(3 downto 0);
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signal nd_modified : std_logic;
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signal nd_modified : std_logic;
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constant period : time := 10 ns;
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constant period : time := 10 ns;
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constant md_period : time := period*16;
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constant md_period : time := period*16;
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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begin
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begin
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Inst_orig: singleDouble_original PORT MAP(
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clk_i => clk,
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ce_i => ce_i,
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rst_i => reset,
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data_i => mdi,
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q_o => q_orig,
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ready_o => nd_orig
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);
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Inst_modified: singleDouble PORT MAP(
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Inst_modified: singleDouble PORT MAP(
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clk_i => clk,
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clk_i => clk,
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ce_i => ce_i,
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ce_i => ce_i,
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rst_i => reset,
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rst_i => reset,
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data_i => mdi,
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data_i => mdi,
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