OpenCores
URL https://opencores.org/ocsvn/manchesterwireless/manchesterwireless/trunk

Subversion Repositories manchesterwireless

[/] [manchesterwireless/] [trunk/] [synthTest.vhd] - Diff between revs 2 and 3

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 3
Line 17... Line 17...
  );
  );
end synthTest;
end synthTest;
 
 
architecture Behavioral of synthTest is
architecture Behavioral of synthTest is
 
 
  component decodeManchester
  component manchesterWireless
  port (
  port (
    clk_i             : in  std_logic;
    clk_i             : in  std_logic;
    rst_i             : in  std_logic;
    rst_i             : in  std_logic;
    data_i            : in  std_logic;
    data_i            : in  std_logic;
    q_o               : out std_logic_vector(WORD_LENGTH-1 downto 0);
    q_o               : out std_logic_vector(WORD_LENGTH-1 downto 0);
Line 30... Line 30...
    waitforstart_rdy : out std_logic
    waitforstart_rdy : out std_logic
  );
  );
  end component;
  end component;
 
 
  signal decode_output : std_logic_vector(WORD_LENGTH-1 downto 0);
  signal decode_output : std_logic_vector(WORD_LENGTH-1 downto 0);
  -- up/down and left/right buffers
 
  signal ud_buff1, ud_buff1_reg : std_logic_vector(6 downto 0);
  signal ud_buff1, ud_buff1_reg : std_logic_vector(6 downto 0);
  signal reset_manchester, soft_reset, ready_o_buff : std_logic;
  signal reset_manchester, soft_reset, ready_o_buff : std_logic;
begin
begin
  character_o(7) <= '1'; -- turn off decimal point
  character_o(7) <= '1'; -- turn off decimal point
  testpin <= '1';
  testpin <= '1';
 
 
  reset_manchester <=  rst_i or soft_reset;
  reset_manchester <=  rst_i or soft_reset;
  ready_o <= ready_o_buff;
  ready_o <= ready_o_buff;
 
 
  inst_decodeManchester: decodeManchester
  inst_manchesterWireless : manchesterWireless
  port map(
  port map(
    clk_i   => clk_i,
    clk_i   => clk_i,
    rst_i   => reset_manchester,
    rst_i   => reset_manchester,
    data_i  => data_i,
    data_i  => data_i,
    q_o     => decode_output,
    q_o     => decode_output,
    ready_o => ready_o_buff,
    ready_o => ready_o_buff,
    recieved_debug => recieved_debug,
    recieved_debug => recieved_debug,
    waitforstart_rdy => waitforstart_rdy
    waitforstart_rdy => waitforstart_rdy
  );
  );
 
 
  -- decode up/down first digit (ones place)
  -- decode digit
  with decode_output(3 downto 0) select
  with decode_output(3 downto 0) select
     ud_buff1  <= "0000001" when x"0",  -- off
     ud_buff1  <= "0000001" when x"0",  -- off
                   "1001111" when x"1",  -- 1
                   "1001111" when x"1",  -- 1
                   "0010010" when x"2",  -- 2
                   "0010010" when x"2",  -- 2
                   "0000110" when x"3",  -- 3
                   "0000110" when x"3",  -- 3

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.