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Saved contents of this file to system_log.71 during revup to EDK 8.1.
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Xilinx Platform Studio (XPS)
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Xilinx Platform Studio (XPS)
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Xilinx EDK 7.1.2 Build EDK_H.12.5.1
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Xilinx EDK 8.1 Build EDK_I.18.7
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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At Local date and time: Fri Jun 23 17:59:37 2006
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xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make clean; exit;" started...
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Created pcores directory
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Copied file bitgen.ut from $XILINX_EDK/data/xflow directory to etc directory
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Copied file bitgen_spartan3.ut from $XILINX_EDK/data directory to etc directory
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Copied file fast_runtime.opt from $XILINX_EDK/data/xflow directory to etc directory
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WARNING:MDT - Created an empty D:\mb-jpeg\data\system.ucf. If your design needs any constraints, please make changes to this UCF file.
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Project Opened.
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Assigned Driver bram 1.00.a for instance lmb_bram_if_cntlr_0
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Assigned Driver bram 1.00.a for instance lmb_bram_if_cntlr_1
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Saving MSS changes, if any.
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Loading Project File..
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No changes to be saved in XMP file
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Project Opened.
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At Local date and time: Fri Jun 23 16:07:28 2006
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Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make netlist; exit;" Started...
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****************************************************
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Creating system netlist for hardware specification..
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****************************************************
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platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst system.mhs
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Release Xilinx EDK 7.1.2 - platgen EDK_H.12.5.1
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Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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Command Line: platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst
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system.mhs
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Parse system.mhs ...
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Read MPD definitions ...
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Sourcing tcl file
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C:/edk/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.
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tcl ...
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Sourcing tcl file
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C:/edk/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl
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...
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Sourcing tcl file
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C:/edk/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if
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_cntlr_v2_1_0.tcl ...
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Sourcing tcl file
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C:/edk/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.
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tcl ...
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Overriding IP level properties ...
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microblaze (microblaze_0) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
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mpd:60 - tool overriding c_family value virtex2 to virtex2p
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microblaze (microblaze_0) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
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mpd:61 - tool overriding c_instance value microblaze to microblaze_0
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microblaze (microblaze_0) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
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mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0
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microblaze (microblaze_0) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.
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mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0
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opb_mdm (debug_module) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38
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- tool overriding c_family value virtex2 to virtex2p
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bram_block (lmb_bram) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
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mpd:39 - tool overriding c_family value virtex2 to virtex2p
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opb_gpio (leds_4bit) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\opb_gpio_v3_01_b\data\opb_gpio_v2_1_0.mpd:
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38 - tool overriding c_family value virtex2 to virtex2p
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opb_gpio (dipsws_4bit) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\opb_gpio_v3_01_b\data\opb_gpio_v2_1_0.mpd:
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38 - tool overriding c_family value virtex2 to virtex2p
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opb_gpio (pushbuttons_5bit) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\opb_gpio_v3_01_b\data\opb_gpio_v2_1_0.mpd:
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38 - tool overriding c_family value virtex2 to virtex2p
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dcm_module (dcm_0) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.
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mpd:56 - tool overriding c_family value virtex2 to virtex2p
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bram_block (data_bram_0) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
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mpd:39 - tool overriding c_family value virtex2 to virtex2p
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bram_block (data_bram_1) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
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mpd:39 - tool overriding c_family value virtex2 to virtex2p
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Performing IP level DRCs on properties...
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Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
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Address Map for Processor microblaze_0
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(0x00000000-0x0000ffff) dlmb_cntlr dlmb
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(0x00000000-0x0000ffff) ilmb_cntlr ilmb
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(0x40000000-0x4000ffff) PushButtons_5Bit mb_opb
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(0x40020000-0x4002ffff) LEDs_4Bit mb_opb
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(0x40040000-0x4004ffff) DIPSWs_4Bit mb_opb
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(0x40600000-0x4060ffff) RS232_Uart_1 mb_opb
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(0x41400000-0x4140ffff) debug_module mb_opb
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(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
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(0x70000000-0x7000ffff) data_bram_if_cntlr_0 dlmb
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(0x70010000-0x7001ffff) data_bram_if_cntlr_1 dlmb
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Check platform configuration ...
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opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:55 - 2 master(s) : 6 slave(s)
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lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:81 - 1 master(s) : 1 slave(s)
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lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:89 - 1 master(s) : 3 slave(s)
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Check port drivers...
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Check platform address map ...
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Overriding system level properties ...
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opb_v20 (mb_opb) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36
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- tool overriding c_num_masters value 4 to 2
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opb_v20 (mb_opb) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:37
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- tool overriding c_num_slaves value 4 to 6
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lmb_v10 (ilmb) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
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- tool overriding c_lmb_num_slaves value 4 to 1
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lmb_v10 (dlmb) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36
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- tool overriding c_lmb_num_slaves value 4 to 3
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lmb_bram_if_cntlr (dlmb_cntlr) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
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_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x70c70000
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lmb_bram_if_cntlr (ilmb_cntlr) -
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C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
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_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x70c70000
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|
bram_block (lmb_bram) -
|
|
C:\edk\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.
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mpd:35 - tool overriding c_memsize value 2048 to 65536
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bram_block (data_bram_0) - D:\mb-jpeg\system.mhs:214 - tool overriding c_memsize
|
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value 16384 to 65536
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lmb_bram_if_cntlr (data_bram_if_cntlr_0) -
|
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C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
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_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x70c70000
|
|
bram_block (data_bram_1) - D:\mb-jpeg\system.mhs:230 - tool overriding c_memsize
|
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value 16384 to 65536
|
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lmb_bram_if_cntlr (data_bram_if_cntlr_1) -
|
|
C:\edk\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if
|
|
_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x70c70000
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|
|
|
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
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|
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Performing System level DRCs on properties...
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|
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Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
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|
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Modify defaults ...
|
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|
|
Processing licensed instances ...
|
|
Completion time: 0.00 seconds
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|
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Creating hardware output directories ...
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|
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Managing hardware (BBD-specified) netlist files ...
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|
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Managing cache ...
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|
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Elaborating instances ...
|
|
bram_block (lmb_bram) - D:\mb-jpeg\system.mhs:115 - elaborating IP
|
|
bram_block (data_bram_0) - D:\mb-jpeg\system.mhs:211 - elaborating IP
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bram_block (data_bram_1) - D:\mb-jpeg\system.mhs:227 - elaborating IP
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Writing HDL for elaborated instances ...
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Inserting wrapper level ...
|
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Completion time: 4.00 seconds
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Constructing platform-level signal connectivity ...
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Completion time: 2.00 seconds
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Writing (top-level) BMM ...
|
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Writing BMM - D:\mb-jpeg\implementation\system.bmm
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Writing (top-level and wrappers) HDL ...
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Generating synthesis project file ...
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|
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Running XST synthesis ...
|
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INFO:MDT - The following instances are synthesized with XST. The MPD option
|
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IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
|
|
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
|
|
microblaze_0_wrapper (microblaze_0) - D:\mb-jpeg\system.mhs:35 - Running XST
|
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synthesis
|
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mb_opb_wrapper (mb_opb) - D:\mb-jpeg\system.mhs:55 - Running XST synthesis
|
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debug_module_wrapper (debug_module) - D:\mb-jpeg\system.mhs:63 - Running XST
|
|
synthesis
|
|
ilmb_wrapper (ilmb) - D:\mb-jpeg\system.mhs:81 - Running XST synthesis
|
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dlmb_wrapper (dlmb) - D:\mb-jpeg\system.mhs:89 - Running XST synthesis
|
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dlmb_cntlr_wrapper (dlmb_cntlr) - D:\mb-jpeg\system.mhs:97 - Running XST
|
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synthesis
|
|
ilmb_cntlr_wrapper (ilmb_cntlr) - D:\mb-jpeg\system.mhs:106 - Running XST
|
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synthesis
|
|
lmb_bram_wrapper (lmb_bram) - D:\mb-jpeg\system.mhs:115 - Running XST synthesis
|
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rs232_uart_1_wrapper (rs232_uart_1) - D:\mb-jpeg\system.mhs:122 - Running XST
|
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synthesis
|
|
sysace_compactflash_wrapper (sysace_compactflash) - D:\mb-jpeg\system.mhs:138 -
|
|
Running XST synthesis
|
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leds_4bit_wrapper (leds_4bit) - D:\mb-jpeg\system.mhs:155 - Running XST
|
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synthesis
|
|
dipsws_4bit_wrapper (dipsws_4bit) - D:\mb-jpeg\system.mhs:169 - Running XST
|
|
synthesis
|
|
pushbuttons_5bit_wrapper (pushbuttons_5bit) - D:\mb-jpeg\system.mhs:183 -
|
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Running XST synthesis
|
|
dcm_0_wrapper (dcm_0) - D:\mb-jpeg\system.mhs:197 - Running XST synthesis
|
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data_bram_0_wrapper (data_bram_0) - D:\mb-jpeg\system.mhs:211 - Running XST
|
|
synthesis
|
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data_bram_if_cntlr_0_wrapper (data_bram_if_cntlr_0) - D:\mb-jpeg\system.mhs:218
|
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- Running XST synthesis
|
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data_bram_1_wrapper (data_bram_1) - D:\mb-jpeg\system.mhs:227 - Running XST
|
|
synthesis
|
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data_bram_if_cntlr_1_wrapper (data_bram_if_cntlr_1) - D:\mb-jpeg\system.mhs:234
|
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- Running XST synthesis
|
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|
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Running NGCBUILD ...
|
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|
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Rebuilding cache ...
|
|
Total run time: 300.00 seconds
|
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Running synthesis...
|
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bash -c "cd synthesis; ./synthesis.sh; cd .."
|
|
WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 33
|
|
days, this program will not operate. For more information about this product,
|
|
please refer to the Evaluation Agreement, which was shipped to you along with
|
|
the Evaluation CDs.
|
|
To purchase an annual license for this software, please contact your local
|
|
Field Applications Engineer (FAE) or salesperson. If you have any questions,
|
|
or if we can assist in any way, please send an email to: eval@xilinx.com
|
|
Thank You!
|
|
Release 7.1.02i - xst H.42
|
|
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
|
-->
|
|
TABLE OF CONTENTS
|
|
1) Synthesis Options Summary
|
|
2) HDL Compilation
|
|
3) HDL Analysis
|
|
4) HDL Synthesis
|
|
5) Advanced HDL Synthesis
|
|
5.1) HDL Synthesis Report
|
|
6) Low Level Synthesis
|
|
7) Final Report
|
|
7.1) Device utilization summary
|
|
7.2) TIMING REPORT
|
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|
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=========================================================================
|
|
* Synthesis Options Summary *
|
|
=========================================================================
|
|
---- Source Parameters
|
|
Input Format : MIXED
|
|
Input File Name : "system_xst.prj"
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|
|
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---- Target Parameters
|
|
Target Device : xc2vp30ff896-7
|
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Output File Name : "../implementation/system.ngc"
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|
|
|
---- Source Options
|
|
Top Module Name : system
|
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|
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---- Target Options
|
|
Add IO Buffers : NO
|
|
|
|
---- General Options
|
|
Optimization Goal : speed
|
|
RTL Output : YES
|
|
Hierarchy Separator : /
|
|
|
|
=========================================================================
|
|
|
|
WARNING:Xst:29 - Optimization Effort not specified
|
|
The following parameters have been added:
|
|
Optimization Effort : 1
|
|
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* HDL Compilation *
|
|
=========================================================================
|
|
Compiling vhdl file "d:/mb-jpeg/synthesis/../hdl/system.vhd" in Library work.
|
|
Entity compiled.
|
|
Entity (Architecture ) compiled.
|
|
|
|
=========================================================================
|
|
* HDL Analysis *
|
|
=========================================================================
|
|
Analyzing Entity (Architecture ).
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1608: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1614: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1620: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1626: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1632: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1638: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1644: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1650: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1656: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1662: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1668: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1676: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1684: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1692: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1700: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1708: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1716: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1724: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1732: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1740: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1748: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1756: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1764: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1772: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1780: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1788: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1796: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1802: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1808: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1814: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1820: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1828: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1836: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1844: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1852: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1860: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1868: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1876: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1884: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1892: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1900: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1908: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1916: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1924: Generating a Black Box for component .
|
|
WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1930: Generating a Black Box for component .
|
|
Entity analyzed. Unit generated.
|
|
|
|
|
|
=========================================================================
|
|
* HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Synthesizing Unit .
|
|
Related source file is "d:/mb-jpeg/synthesis/../hdl/system.vhd".
|
|
Unit synthesized.
|
|
|
|
|
|
=========================================================================
|
|
* Advanced HDL Synthesis *
|
|
=========================================================================
|
|
|
|
Advanced RAM inference ...
|
|
Advanced multiplier inference ...
|
|
Advanced Registered AddSub inference ...
|
|
Dynamic shift register inference ...
|
|
|
|
=========================================================================
|
|
HDL Synthesis Report
|
|
|
|
Found no macro
|
|
=========================================================================
|
|
|
|
=========================================================================
|
|
* Low Level Synthesis *
|
|
=========================================================================
|
|
Loading device for application Rf_Device from file '2vp30.nph' in environment c:/ISE.
|
|
|
|
Optimizing unit ...
|
|
|
|
Mapping all equations...
|
|
Building and optimizing final netlist ...
|
|
|
|
=========================================================================
|
|
* Final Report *
|
|
=========================================================================
|
|
Final Results
|
|
RTL Top Level Output File Name : ../implementation/system.ngr
|
|
Top Level Output File Name : ../implementation/system.ngc
|
|
Output Format : ngc
|
|
Optimization Goal : speed
|
|
Keep Hierarchy : no
|
|
|
|
Design Statistics
|
|
# IOs : 45
|
|
|
|
Cell Usage :
|
|
# BELS : 2
|
|
# GND : 1
|
|
# VCC : 1
|
|
# IO Buffers : 45
|
|
# IBUF : 4
|
|
# IBUFG : 1
|
|
# IOBUF : 29
|
|
# OBUF : 11
|
|
# Others : 18
|
|
# data_bram_0_wrapper : 1
|
|
# data_bram_1_wrapper : 1
|
|
# data_bram_if_cntlr_0_wrapper: 1
|
|
# data_bram_if_cntlr_1_wrapper: 1
|
|
# dcm_0_wrapper : 1
|
|
# debug_module_wrapper : 1
|
|
# dipsws_4bit_wrapper : 1
|
|
# dlmb_cntlr_wrapper : 1
|
|
# dlmb_wrapper : 1
|
|
# ilmb_cntlr_wrapper : 1
|
|
# ilmb_wrapper : 1
|
|
# leds_4bit_wrapper : 1
|
|
# lmb_bram_wrapper : 1
|
|
# mb_opb_wrapper : 1
|
|
# microblaze_0_wrapper : 1
|
|
# pushbuttons_5bit_wrapper : 1
|
|
# rs232_uart_1_wrapper : 1
|
|
# sysace_compactflash_wrapper : 1
|
|
=========================================================================
|
|
|
|
Device utilization summary:
|
|
---------------------------
|
|
|
|
Selected Device : 2vp30ff896-7
|
|
|
|
Number of bonded IOBs: 45 out of 556 8%
|
|
|
|
=========================================================================
|
|
TIMING REPORT
|
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
|
Clock Information:
|
|
------------------
|
|
No clock signals found in this design
|
|
|
|
Timing Summary:
|
|
---------------
|
|
Speed Grade: -7
|
|
|
|
Minimum period: No path found
|
|
Minimum input arrival time before clock: No path found
|
|
Maximum output required time after clock: No path found
|
|
Maximum combinational path delay: 2.924ns
|
|
|
|
Timing Detail:
|
|
--------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
=========================================================================
|
|
Timing constraint: Default path analysis
|
|
Total number of paths / destination ports: 2006 / 1977
|
|
-------------------------------------------------------------------------
|
|
Delay: 2.924ns (Levels of Logic = 1)
|
|
Source: sysace_compactflash:SysACE_MPD_O<3> (PAD)
|
|
Destination: fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> (PAD)
|
|
|
|
Data Path: sysace_compactflash:SysACE_MPD_O<3> to fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
sysace_compactflash_wrapper:SysACE_MPD_O<3> 1 0.000 0.332 sysace_compactflash (fpga_0_SysACE_CompactFlash_SysACE_MPD_O<3>)
|
|
IOBUF:I->IO 2.592 iobuf_22 (fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3>)
|
|
----------------------------------------
|
|
Total 2.924ns (2.592ns logic, 0.332ns route)
|
|
(88.7% logic, 11.3% route)
|
|
|
|
=========================================================================
|
|
CPU : 10.82 / 10.98 s | Elapsed : 11.00 / 11.00 s
|
|
|
|
-->
|
|
|
|
Total memory usage is 160856 kilobytes
|
|
|
|
Number of errors : 0 ( 0 filtered)
|
|
Number of warnings : 47 ( 0 filtered)
|
|
Number of infos : 0 ( 0 filtered)
|
|
Done.
|
|
At Local date and time: Fri Jun 23 16:12:51 2006
|
|
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make bits; exit;" Started...
|
|
Copying Xilinx Implementation tool scripts..
|
|
*********************************************
|
|
Running Xilinx Implementation tools..
|
|
*********************************************
|
|
xflow -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt system.ngc
|
|
Release 7.1.02i - Xflow H.38
|
|
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
|
xflow.exe -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt
|
|
system.ngc
|
|
.... Copying flowfile c:/ISE/xilinx/data/fpga.flw into working directory
|
|
D:/mb-jpeg/implementation
|
|
|
|
Using Flow File: D:/mb-jpeg/implementation/fpga.flw
|
|
Using Option File(s):
|
|
D:/mb-jpeg/implementation/fast_runtime.opt
|
|
|
|
Creating Script File ...
|
|
|
|
#----------------------------------------------#
|
|
# Starting program ngdbuild
|
|
# ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm
|
|
D:/mb-jpeg/implementation/system.ngc -uc system.ucf system.ngd
|
|
#----------------------------------------------#
|
|
Release 7.1.02i - ngdbuild H.42
|
|
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
|
|
|
Command Line: ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm -uc
|
|
system.ucf D:/mb-jpeg/implementation/system.ngc system.ngd
|
|
|
|
Reading NGO file 'D:/mb-jpeg/implementation/system.ngc' ...
|
|
Loading design module "D:/mb-jpeg/implementation/microblaze_0_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/mb_opb_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/debug_module_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/ilmb_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/dlmb_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/dlmb_cntlr_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/ilmb_cntlr_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/lmb_bram_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/rs232_uart_1_wrapper.ngc"...
|
|
Loading design module
|
|
"D:/mb-jpeg/implementation/sysace_compactflash_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/leds_4bit_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/dipsws_4bit_wrapper.ngc"...
|
|
Loading design module
|
|
"D:/mb-jpeg/implementation/pushbuttons_5bit_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/dcm_0_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/data_bram_0_wrapper.ngc"...
|
|
Loading design module
|
|
"D:/mb-jpeg/implementation/data_bram_if_cntlr_0_wrapper.ngc"...
|
|
Loading design module "D:/mb-jpeg/implementation/data_bram_1_wrapper.ngc"...
|
|
Loading design module
|
|
"D:/mb-jpeg/implementation/data_bram_if_cntlr_1_wrapper.ngc"...
|
|
|
|
Applying constraints in "system.ucf" to the design...
|
|
|
|
Checking timing specifications ...
|
|
INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification
|
|
"TS_sys_clk_pin", was traced into DCM instance "dcm_0/dcm_0/DCM_INST". The
|
|
following new TNM groups and period specifications were generated at the DCM
|
|
output(s):
|
|
CLK0: TS_dcm_0_dcm_0_CLK0_BUF=PERIOD dcm_0_dcm_0_CLK0_BUF
|
|
TS_sys_clk_pin*1.000000 HIGH 50.000000%
|
|
|
|
Processing BMM file ...
|
|
|
|
Checking expanded design ...
|
|
WARNING:NgdBuild:452 - logical net
|
|
'microblaze_0/microblaze_0/Data_Flow_I/word_r1_r2_unalignment' has no driver
|
|
WARNING:NgdBuild:452 - logical net
|
|
'microblaze_0/microblaze_0/Data_Flow_I/word_r1_imm_unalignment' has no driver
|
|
WARNING:NgdBuild:452 - logical net
|
|
'microblaze_0/microblaze_0/Data_Flow_I/halfword_unalignment' has no driver
|
|
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
|
|
debug_module/debug_module/BUFG_DRCK1 drives no clock pins
|
|
|
|
NGDBUILD Design Results Summary:
|
|
Number of errors: 0
|
|
Number of warnings: 4
|
|
|
|
Writing NGD file "system.ngd" ...
|
|
|
|
Writing NGDBUILD log file "system.bld"...
|
|
|
|
NGDBUILD done.
|
|
|
|
|
|
|
|
#----------------------------------------------#
|
|
# Starting program map
|
|
# map -o system_map.ncd -pr b system.ngd system.pcf
|
|
#----------------------------------------------#
|
|
Release 7.1.02i - Map H.42
|
|
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
|
Using target part "2vp30ff896-7".
|
|
Mapping design into LUTs...
|
|
Writing file system_map.ngm...
|
|
Running directed packing...
|
|
Running delay-based LUT packing...
|
|
Running related packing...
|
|
Writing design file "system_map.ncd"...
|
|
|
|
Design Summary:
|
|
Number of errors: 0
|
|
Number of warnings: 8
|
|
Logic Utilization:
|
|
Number of Slice Flip Flops: 1,186 out of 27,392 4%
|
|
Number of 4 input LUTs: 1,466 out of 27,392 5%
|
|
Logic Distribution:
|
|
Number of occupied Slices: 1,296 out of 13,696 9%
|
|
Number of Slices containing only related logic: 1,296 out of 1,296 100%
|
|
Number of Slices containing unrelated logic: 0 out of 1,296 0%
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
|
Total Number 4 input LUTs: 1,899 out of 27,392 6%
|
|
Number used as logic: 1,466
|
|
Number used as a route-thru: 15
|
|
Number used for Dual Port RAMs: 256
|
|
(Two LUTs used per Dual Port RAM)
|
|
Number used as Shift registers: 162
|
|
|
|
Number of bonded IOBs: 44 out of 556 7%
|
|
IOB Flip Flops: 73
|
|
Number of PPC405s: 0 out of 2 0%
|
|
Number of Block RAMs: 96 out of 136 70%
|
|
Number of MULT18X18s: 3 out of 136 2%
|
|
Number of GCLKs: 2 out of 16 12%
|
|
Number of DCMs: 1 out of 8 12%
|
|
Number of BSCANs: 1 out of 1 100%
|
|
Number of GTs: 0 out of 8 0%
|
|
Number of GT10s: 0 out of 0 0%
|
|
|
|
Number of RPM macros: 5
|
|
Total equivalent gate count for design: 6,374,492
|
|
Additional JTAG gate count for IOBs: 2,112
|
|
Peak Memory Usage: 193 MB
|
|
|
|
NOTES:
|
|
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
|
Map gives priority to combine logic that is related. Doing so results in
|
|
the best timing performance.
|
|
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
|
related logic packing.
|
|
|
|
Note that once logic distribution reaches the 99% level through related
|
|
logic packing, this does not mean the device is completely utilized.
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
|
unrelated logic packing may adversely affect the overall timing performance
|
|
of your design.
|
|
|
|
Mapping completed.
|
|
See MAP report file "system_map.mrp" for details.
|
|
|
|
|
|
|
|
#----------------------------------------------#
|
|
# Starting program par
|
|
# par -w -ol high system_map.ncd system.ncd system.pcf
|
|
#----------------------------------------------#
|
|
Release 7.1.02i - par H.42
|
|
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
|
|
|
|
|
|
|
Constraints file: system.pcf.
|
|
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 33
|
|
days, this program will not operate. For more information about this product,
|
|
please refer to the Evaluation Agreement, which was shipped to you along with
|
|
the Evaluation CDs.
|
|
To purchase an annual license for this software, please contact your local
|
|
Field Applications Engineer (FAE) or salesperson. If you have any questions,
|
|
or if we can assist in any way, please send an email to: eval@xilinx.com
|
|
Thank You!
|
|
Loading device for application Rf_Device from file '2vp30.nph' in environment
|
|
c:/ISE.
|
|
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
|
|
|
|
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000
|
|
Celsius)
|
|
Initializing voltage to 1.500 Volts. (default - Range: 1.400 to 1.600 Volts)
|
|
|
|
Device speed data version: "PRODUCTION 1.91 2005-07-22".
|
|
|
|
|
|
Device Utilization Summary:
|
|
|
|
Number of BSCANs 1 out of 1 100%
|
|
Number of BUFGMUXs 2 out of 16 12%
|
|
Number of DCMs 1 out of 8 12%
|
|
Number of External IOBs 44 out of 556 7%
|
|
Number of LOCed IOBs 44 out of 44 100%
|
|
|
|
Number of MULT18X18s 3 out of 136 2%
|
|
Number of RAMB16s 96 out of 136 70%
|
|
Number of SLICEs 1296 out of 13696 9%
|
|
|
|
|
|
Overall effort level (-ol): High (set by user)
|
|
Placer effort level (-pl): High (set by user)
|
|
Placer cost table entry (-t): 1
|
|
Router effort level (-rl): High (set by user)
|
|
|
|
Starting initial Timing Analysis. REAL time: 6 secs
|
|
Finished initial Timing Analysis. REAL time: 7 secs
|
|
|
|
|
|
Starting Placer
|
|
|
|
Phase 1.1
|
|
Phase 1.1 (Checksum:9b1b32) REAL time: 9 secs
|
|
|
|
Phase 2.31
|
|
Phase 2.31 (Checksum:1312cfe) REAL time: 9 secs
|
|
|
|
WARNING:Place:414 - The input design contains local clock signal(s). To get the
|
|
better result, we recommend users run map with the "-timing" option set
|
|
before starting the placement.
|
|
Phase 3.2
|
|
.
|
|
|
|
|
|
Phase 3.2 (Checksum:1c9c37d) REAL time: 15 secs
|
|
|
|
Phase 4.30
|
|
Phase 4.30 (Checksum:26259fc) REAL time: 15 secs
|
|
|
|
Phase 5.3
|
|
Phase 5.3 (Checksum:2faf07b) REAL time: 16 secs
|
|
|
|
Phase 6.5
|
|
Phase 6.5 (Checksum:39386fa) REAL time: 16 secs
|
|
|
|
Phase 7.8
|
|
.......................................................
|
|
.......
|
|
........................................................
|
|
.........
|
|
.......
|
|
Phase 7.8 (Checksum:1036ece) REAL time: 30 secs
|
|
|
|
Phase 8.5
|
|
Phase 8.5 (Checksum:4c4b3f8) REAL time: 30 secs
|
|
|
|
Phase 9.18
|
|
Phase 9.18 (Checksum:55d4a77) REAL time: 37 secs
|
|
|
|
Phase 10.5
|
|
Phase 10.5 (Checksum:5f5e0f6) REAL time: 37 secs
|
|
|
|
Phase 11.27
|
|
Phase 11.27 (Checksum:68e7775) REAL time: 38 secs
|
|
|
|
Phase 12.24
|
|
Phase 12.24 (Checksum:7270df4) REAL time: 38 secs
|
|
Writing design to file system.ncd
|
|
|
|
|
|
Total REAL time to Placer completion: 41 secs
|
|
Total CPU time to Placer completion: 35 secs
|
|
|
|
Starting Router
|
|
Phase 1: 15230 unrouted; REAL time: 53 secs
|
|
Phase 2: 13515 unrouted; REAL time: 54 secs
|
|
Phase 3: 3706 unrouted; REAL time: 1 mins
|
|
|
|
Phase 4: 3706 unrouted; (71354) REAL time: 1 mins 1 secs
|
|
Phase 5: 3783 unrouted; (306) REAL time: 1 mins 14 secs
|
|
Phase 6: 3788 unrouted; (0) REAL time: 1 mins 19 secs
|
|
Phase 7: 0 unrouted; (0) REAL time: 1 mins 35 secs
|
|
Phase 8: 0 unrouted; (0) REAL time: 1 mins 38 secs
|
|
|
|
Total REAL time to Router completion: 1 mins 44 secs
|
|
Total CPU time to Router completion: 1 mins 32 secs
|
|
|
|
Generating "PAR" statistics.
|
|
|
|
**************************
|
|
Generating Clock Report
|
|
**************************
|
|
|
|
+---------------------+--------------+------+------+------------+-------------+
|
|
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
|
+---------------------+--------------+------+------+------------+-------------+
|
|
|data_bram_0_port_BRA | | | | | |
|
|
| M_Clk | BUFGMUX7S| No | 943 | 0.281 | 1.258 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
|
| DBG_CLK_s | BUFGMUX4P| No | 139 | 0.267 | 1.257 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
|
|fpga_0_SysACE_Compac | | | | | |
|
|
| tFlash_SysACE_CLK | Local| | 65 | 0.281 | 2.475 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
|
|debug_module/bscan_u | | | | | |
|
|
| pdate | Local| | 1 | 0.000 | 0.356 |
|
|
+---------------------+--------------+------+------+------------+-------------+
|
|
Timing Score: 0
|
|
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
|
This may be due to a setup or hold violation.
|
|
|
|
--------------------------------------------------------------------------------
|
|
Constraint | Requested | Actual | Logic
|
|
| | | Levels
|
|
--------------------------------------------------------------------------------
|
|
NET "fpga_0_SysACE_CompactFlash_SysACE_CL | 30.000ns | 4.555ns | 2
|
|
K" PERIOD = 30 ns HIGH 50% | | |
|
|
--------------------------------------------------------------------------------
|
|
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A | N/A | N/A
|
|
pin" 10 ns HIGH 50% | | |
|
|
--------------------------------------------------------------------------------
|
|
TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 10.000ns | 9.935ns | 11
|
|
"dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin | | |
|
|
HIGH 50% | | |
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
All constraints were met.
|
|
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
|
|
constraint does not cover any paths or that it has no requested value.
|
|
Generating Pad Report.
|
|
|
|
All signals are completely routed.
|
|
|
|
Total REAL time to PAR completion: 1 mins 48 secs
|
|
Total CPU time to PAR completion: 1 mins 36 secs
|
|
|
|
Peak Memory Usage: 246 MB
|
|
|
|
Placement: Completed - No errors found.
|
|
Routing: Completed - No errors found.
|
|
Timing: Completed - No errors found.
|
|
|
|
Number of error messages: 0
|
|
Number of warning messages: 2
|
|
Number of info messages: 0
|
|
|
|
Writing design to file system.ncd
|
|
|
|
|
|
PAR done!
|
|
|
|
|
|
|
|
#----------------------------------------------#
|
|
# Starting program post_par_trce
|
|
# trce -e 3 -xml system.twx system.ncd system.pcf
|
|
#----------------------------------------------#
|
|
Release 7.1.02i - Trace H.42
|
|
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
|
|
|
|
|
Loading device for application Rf_Device from file '2vp30.nph' in environment
|
|
c:/ISE.
|
|
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
|
|
--------------------------------------------------------------------------------
|
|
Release 7.1.02i Trace H.42
|
|
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
|
|
|
trce -e 3 -xml system.twx system.ncd system.pcf
|
|
|
|
|
|
Design file: system.ncd
|
|
Physical constraint file: system.pcf
|
|
Device,speed: xc2vp30,-7 (PRODUCTION 1.91 2005-07-22)
|
|
Report level: error report
|
|
--------------------------------------------------------------------------------
|
|
|
|
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
|
option. All paths that are not constrained will be reported in the
|
|
unconstrained paths section(s) of the report.
|
|
|
|
|
|
Timing summary:
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0
|
|
|
|
Constraints cover 475026 paths, 0 nets, and 12068 connections
|
|
|
|
Design statistics:
|
|
Minimum period: 9.935ns (Maximum frequency: 100.654MHz)
|
|
|
|
|
|
Analysis completed Fri Jun 23 16:15:21 2006
|
|
--------------------------------------------------------------------------------
|
|
|
|
Generating Report ...
|
|
|
|
Number of warnings: 0
|
|
Number of info messages: 1
|
|
Total time: 10 secs
|
|
|
|
|
|
xflow done!
|
|
cd implementation; bitgen -w -f bitgen.ut system
|
|
Release 7.1.02i - Bitgen H.42
|
|
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
|
|
Loading device for application Rf_Device from file '2vp30.nph' in environment
|
|
c:/ISE.
|
|
"system" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7
|
|
Opened constraints file system.pcf.
|
|
|
|
Fri Jun 23 16:15:26 2006
|
|
Running DRC.
|
|
WARNING:PhysDesignRules:367 - The signal is
|
|
incomplete. The signal does not drive any load pins in the design.
|
|
DRC detected 0 errors and 1 warnings.
|
|
Creating bit map...
|
|
Saving bit stream in "system.bit".
|
|
Creating bit mask...
|
|
Saving mask bit stream in "system.msk".
|
|
Bitstream generation is complete.
|
|
Done.
|
|
At Local date and time: Fri Jun 23 16:18:55 2006
|
|
Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make clean; exit;" Started...
|
|
rm -f implementation/system.ngc
|
rm -f implementation/system.ngc
|
|
|
|
|
rm -f implementation/system.bmm
|
rm -f implementation/system.bmm
|
rm -f implementation/system.bit
|
rm -f implementation/system.bit
|
|
|
|
|
rm -f implementation/system.ncd
|
rm -f implementation/system.ncd
|
rm -f implementation/system_bd.bmm
|
rm -f implementation/system_bd.bmm
|
|
|
|
|
rm -rf implementation synthesis xst hdl
|
rm -rf implementation synthesis xst hdl
|
rm -rf xst.srp system.srp
|
rm -rf xst.srp system.srp
|
|
|
|
|
rm -rf microblaze_0/lib/
|
rm -rf microblaze_0/lib/
|
rm -f decoder/executable.elf
|
rm -f decoder/executable.elf
|
|
|
|
|
rm -rf simulation/behavioral
|
rm -rf simulation/behavioral
|
rm -rf virtualplatform
|
rm -rf virtualplatform
|
rm -f _impact.cmd
|
rm -f _impact.cmd
|
Done.
|
|
|
|
|
|
|
|
|
Done!
|
|
|