Subversion Repositories mb-jpeg

Xilinx Platform Studio (XPS)

Xilinx EDK 7.1.2 Build EDK_H.12.5.1

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Copied file bitgen.ut from $XILINX_EDK/data/xflow directory to etc directory

Copied file bitgen_spartan3.ut from $XILINX_EDK/data directory to etc directory

Copied file fast_runtime.opt from $XILINX_EDK/data/xflow directory to etc directory

WARNING:MDT - Created an empty D:\mb-jpeg\data\system.ucf. If your design needs any constraints, please make changes to this UCF file.

Project Opened.

No changes to be saved in XMP file

Xilinx Platform Studio (XPS)

Xilinx EDK 7.1.2 Build EDK_H.12.5.1

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

At Local date and time: Wed Nov 01 18:28:08 2006

Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...

*********************************************

Creating software libraries...

*********************************************

libgen -mhs system.mhs -p xc2vp30ff896-7 -lp D:/XilinxXUP/lib/  system.mss

libgen

Xilinx EDK 7.1.2 Build EDK_H.12.5.1

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: libgen -mhs system.mhs -p xc2vp30ff896-7 -lp D:/XilinxXUP/lib/

system.mss

Output Directory (-od)          : D:\mb-jpeg\

Part (-p)                       : virtex2p

Software Specification file     : system.mss

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.

tcl ...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl

...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if

_cntlr_v2_1_0.tcl ...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.

tcl ...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl

...

Overriding IP level properties ...

microblaze (microblaze_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.

mpd:60 - tool overriding c_family value virtex2 to virtex2p

microblaze (microblaze_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.

mpd:61 - tool overriding c_instance value microblaze to microblaze_0

microblaze (microblaze_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.

mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0

microblaze (microblaze_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.

mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0

opb_mdm (debug_module) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38

- tool overriding c_family value virtex2 to virtex2p

bram_block (lmb_bram) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.

mpd:39 - tool overriding c_family value virtex2 to virtex2p

opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42

- tool overriding c_family value virtex2 to virtex2p

dcm_module (dcm_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.

mpd:56 - tool overriding c_family value virtex2 to virtex2p

dcm_module (dcm_1) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.

mpd:56 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0x00000000-0x00001fff) dlmb_cntlr    dlmb

  (0x00000000-0x00001fff) ilmb_cntlr    ilmb

  (0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5      mb_opb

  (0x40600000-0x4060ffff) RS232_Uart_1  mb_opb

  (0x41400000-0x4140ffff) debug_module  mb_opb

  (0x41800000-0x4180ffff) SysACE_CompactFlash   mb_opb

Check platform configuration ...

opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:74 - 2 master(s) : 4 slave(s)

lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:100 - 1 master(s) : 1 slave(s)

lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:108 - 1 master(s) : 1 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...

opb_v20 (mb_opb) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36

- tool overriding c_num_masters value 4 to 2

lmb_v10 (ilmb) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36

- tool overriding c_lmb_num_slaves value 4 to 1

lmb_v10 (dlmb) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36

- tool overriding c_lmb_num_slaves value 4 to 1

lmb_bram_if_cntlr (dlmb_cntlr) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if

_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000

lmb_bram_if_cntlr (ilmb_cntlr) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if

_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000

bram_block (lmb_bram) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.

mpd:35 - tool overriding c_memsize value 2048 to 8192

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...

Performing System level DRCs on properties...

WARNING:MDT - Peripheral sysclk_inv is not connected to any of the processors in

   the system. Check for the following reasons.

   1. sysclk_inv is not connected to any of the buses connected to a processor.

   2. sysclk_inv does not have adresses set correctly.

   3. sysclk_inv's address is not within any of the bridge windows connected to

   a processor.

WARNING:MDT - Peripheral clk90_inv is not connected to any of the processors in

   the system. Check for the following reasons.

   1. clk90_inv is not connected to any of the buses connected to a processor.

   2. clk90_inv does not have adresses set correctly.

   3. clk90_inv's address is not within any of the bridge windows connected to a

   processor.

WARNING:MDT - Peripheral ddr_clk90_inv is not connected to any of the processors

   in the system. Check for the following reasons.

   1. ddr_clk90_inv is not connected to any of the buses connected to a

   processor.

   2. ddr_clk90_inv does not have adresses set correctly.

   3. ddr_clk90_inv's address is not within any of the bridge windows connected

   to a processor.

WARNING:MDT - Peripheral dcm_0 is not connected to any of the processors in the

   system. Check for the following reasons.

   1. dcm_0 is not connected to any of the buses connected to a processor.

   2. dcm_0 does not have adresses set correctly.

   3. dcm_0's address is not within any of the bridge windows connected to a

   processor.

WARNING:MDT - Peripheral dcm_1 is not connected to any of the processors in the

   system. Check for the following reasons.

   1. dcm_1 is not connected to any of the buses connected to a processor.

   2. dcm_1 does not have adresses set correctly.

   3. dcm_1's address is not within any of the bridge windows connected to a

   processor.

INFO:MDT - List of peripherals addressable from processor instance microblaze_0

   :

  - dlmb_cntlr

  - ilmb_cntlr

  - debug_module

  - RS232_Uart_1

  - SysACE_CompactFlash

  - DDR_256MB_32MX64_rank1_row13_col10_cl2_5

Building Directory Structure for microblaze_0

Generating platform libraries and device drivers ...

Running CopyFiles ...

Copying files for os standalone_v1_00_a from

C:\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to

D:\mb-jpeg\microblaze_0\libsrc\standalone_v1_00_a\ ...

Copying files for driver uartlite_v1_00_b from

C:\EDK\sw\XilinxProcessorIPLib\drivers\uartlite_v1_00_b\src\ to

D:\mb-jpeg\microblaze_0\libsrc\uartlite_v1_00_b\ ...

Copying files for driver sysace_v1_00_a from

C:\EDK\sw\XilinxProcessorIPLib\drivers\sysace_v1_00_a\src\ to

D:\mb-jpeg\microblaze_0\libsrc\sysace_v1_00_a\ ...

Copying files for driver cpu_v1_00_a from

C:\EDK\sw\XilinxProcessorIPLib\drivers\cpu_v1_00_a\src\ to

D:\mb-jpeg\microblaze_0\libsrc\cpu_v1_00_a\ ...

Running DRCs for OSes, Drivers and Libraries ...

Running generate for OS'es, Drivers and Libraries ...

Copying Library Files ...

Running post_generate for OS'es, Drivers and Libraries ...

Running make for Drivers and Libraries ...

Configuring make for target include using:

make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"

"COMPILER_FLAGS=-mno-xl-soft-mul  -O2 -c" "EXTRA_COMPILER_FLAGS=-g"

Configuring make for target libs using:

make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"

"COMPILER_FLAGS=-mno-xl-soft-mul  -O2 -c" "EXTRA_COMPILER_FLAGS=-g"

Compiling commo

Compiling  microblaze_disable_dcache.

Compiling  microblaze_disable_exceptions.

Compiling  microblaze_disable_icache.

Compiling  microblaze_disable_interrupts.

Compiling  microblaze_enable_dcache.

Compiling  microblaze_enable_exceptions.

Compiling  microblaze_enable_icache.

Compiling  microblaze_enable_interrupts.

Compiling  microblaze_init_dcache_range.

Compiling  microblaze_init_icache_range.

Compiling  microblaze_update_dcache.

Compiling  microblaze_update_icache.

Compiling  inbyte.

Compiling  microblaze_exception_handler.

Compiling  microblaze_exceptions_g.

Compiling  microblaze_interrupt_handler.

Compiling  microblaze_interrupts_g.

Compiling  outbyte.

Compiling  hw_exception_handler.

Compiling uartlit

Compiling sysac

Compiling cp

Libraries generated in D:\mb-jpeg\microblaze_0\lib\ directory

Running execs_generate for OS'es, Drivers and Libraries ...

LibGen Done.

mb-gcc -O2 TestApp_Memory/src/TestApp_Memory.c  -o TestApp_Memory/executable.elf \

   -mno-xl-soft-mul     -Wl,-T -Wl,TestApp_Memory/src/TestApp_Memory_LinkScr  -g   -I./microblaze_0/include/  -L./microblaze_0/lib/  \

-xl-mode-executable  \

mb-size TestApp_Memory/executable.elf

   text    data     bss     dec     hex filename

   3768     324       8    4100    1004 TestApp_Memory/executable.elf

Done.

At Local date and time: Wed Nov 01 18:28:27 2006

Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...

make: Nothing to be done for `program'.

Done.

At Local date and time: Wed Nov 01 18:28:36 2006

Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make bits; exit;" Started...

****************************************************

Creating system netlist for hardware specification..

****************************************************

platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/  -st xst system.mhs

Release Xilinx EDK 7.1.2 - platgen EDK_H.12.5.1

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst

system.mhs

Parse system.mhs ...

Read MPD definitions ...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.

tcl ...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl

...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if

_cntlr_v2_1_0.tcl ...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.

tcl ...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl

...

Overriding IP level properties ...

microblaze (microblaze_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.

mpd:60 - tool overriding c_family value virtex2 to virtex2p

microblaze (microblaze_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.

mpd:61 - tool overriding c_instance value microblaze to microblaze_0

microblaze (microblaze_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.

mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0

microblaze (microblaze_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.

mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0

opb_mdm (debug_module) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38

- tool overriding c_family value virtex2 to virtex2p

bram_block (lmb_bram) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.

mpd:39 - tool overriding c_family value virtex2 to virtex2p

opb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42

- tool overriding c_family value virtex2 to virtex2p

dcm_module (dcm_0) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.

mpd:56 - tool overriding c_family value virtex2 to virtex2p

dcm_module (dcm_1) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.

mpd:56 - tool overriding c_family value virtex2 to virtex2p

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0x00000000-0x00001fff) dlmb_cntlr    dlmb

  (0x00000000-0x00001fff) ilmb_cntlr    ilmb

  (0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5      mb_opb

  (0x40600000-0x4060ffff) RS232_Uart_1  mb_opb

  (0x41400000-0x4140ffff) debug_module  mb_opb

  (0x41800000-0x4180ffff) SysACE_CompactFlash   mb_opb

Check platform configuration ...

opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:74 - 2 master(s) : 4 slave(s)

lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:100 - 1 master(s) : 1 slave(s)

lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:108 - 1 master(s) : 1 slave(s)

Check port drivers...

Check platform address map ...

Overriding system level properties ...

opb_v20 (mb_opb) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36

- tool overriding c_num_masters value 4 to 2

lmb_v10 (ilmb) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36

- tool overriding c_lmb_num_slaves value 4 to 1

lmb_v10 (dlmb) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36

- tool overriding c_lmb_num_slaves value 4 to 1

lmb_bram_if_cntlr (dlmb_cntlr) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if

_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000

lmb_bram_if_cntlr (ilmb_cntlr) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if

_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000

bram_block (lmb_bram) -

C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.

mpd:35 - tool overriding c_memsize value 2048 to 8192

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...

Performing System level DRCs on properties...

Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

Sourcing tcl file

C:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...

INFO: The DDR_256MB_32MX64_rank1_row13_col10_cl2_5 core has constraints automatically generated by XPS in implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ucf.

It can be overridden by constraints placed in the system.ucf file.

Modify defaults ...

Processing licensed instances ...

Completion time: 0.00 seconds

Creating hardware output directories ...

Managing hardware (BBD-specified) netlist files ...

Managing cache ...

Elaborating instances ...

bram_block (lmb_bram) - D:\mb-jpeg\system.mhs:134 - elaborating IP

Writing HDL for elaborated instances ...

Inserting wrapper level ...

Completion time: 4.00 seconds

Constructing platform-level signal connectivity ...

Completion time: 3.00 seconds

Writing (top-level) BMM ...

Writing BMM - D:\mb-jpeg\implementation\system.bmm

Writing (top-level and wrappers) HDL ...

Generating synthesis project file ...

Running XST synthesis ...

INFO:MDT - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.

microblaze_0_wrapper (microblaze_0) - D:\mb-jpeg\system.mhs:54 - Running XST

synthesis

mb_opb_wrapper (mb_opb) - D:\mb-jpeg\system.mhs:74 - Running XST synthesis

debug_module_wrapper (debug_module) - D:\mb-jpeg\system.mhs:82 - Running XST

synthesis

ilmb_wrapper (ilmb) - D:\mb-jpeg\system.mhs:100 - Running XST synthesis

dlmb_wrapper (dlmb) - D:\mb-jpeg\system.mhs:108 - Running XST synthesis

dlmb_cntlr_wrapper (dlmb_cntlr) - D:\mb-jpeg\system.mhs:116 - Running XST

synthesis

ilmb_cntlr_wrapper (ilmb_cntlr) - D:\mb-jpeg\system.mhs:125 - Running XST

synthesis

lmb_bram_wrapper (lmb_bram) - D:\mb-jpeg\system.mhs:134 - Running XST synthesis

rs232_uart_1_wrapper (rs232_uart_1) - D:\mb-jpeg\system.mhs:141 - Running XST

synthesis

sysace_compactflash_wrapper (sysace_compactflash) - D:\mb-jpeg\system.mhs:157 -

Running XST synthesis

ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper

(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:174 - Running

XST synthesis

sysclk_inv_wrapper (sysclk_inv) - D:\mb-jpeg\system.mhs:218 - Running XST

synthesis

clk90_inv_wrapper (clk90_inv) - D:\mb-jpeg\system.mhs:227 - Running XST

synthesis

ddr_clk90_inv_wrapper (ddr_clk90_inv) - D:\mb-jpeg\system.mhs:236 - Running XST

synthesis

dcm_0_wrapper (dcm_0) - D:\mb-jpeg\system.mhs:245 - Running XST synthesis

dcm_1_wrapper (dcm_1) - D:\mb-jpeg\system.mhs:261 - Running XST synthesis

Running NGCBUILD ...

ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper

(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:174 - Running

NGCBUILD

Rebuilding cache ...

Total run time: 282.00 seconds

Running synthesis...

bash -c "cd synthesis; ./synthesis.sh; cd .."

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 17

   days, this program will not operate. For more information about this product,

   please refer to the Evaluation Agreement, which was shipped to you along with

   the Evaluation CDs.

   To purchase an annual license for this software, please contact your local

   Field Applications Engineer (FAE) or salesperson. If you have any questions,

   or if we can assist in any way, please send an email to: eval@xilinx.com

   Thank You!

Release 7.1.02i - xst H.42

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

-->

TABLE OF CONTENTS

  1) Synthesis Options Summary

  2) HDL Compilation

  3) HDL Analysis

  4) HDL Synthesis

  5) Advanced HDL Synthesis

     5.1) HDL Synthesis Report

  6) Low Level Synthesis

  7) Final Report

     7.1) Device utilization summary

     7.2) TIMING REPORT

=========================================================================

*                      Synthesis Options Summary                        *

=========================================================================

---- Source Parameters

Input Format                       : MIXED

Input File Name                    : "system_xst.prj"

---- Target Parameters

Target Device                      : xc2vp30ff896-7

Output File Name                   : "../implementation/system.ngc"

---- Source Options

Top Module Name                    : system

---- Target Options

Add IO Buffers                     : NO

---- General Options

Optimization Goal                  : speed

RTL Output                         : YES

Hierarchy Separator                : /

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified

The following parameters have been added:

Optimization Effort                : 1

=========================================================================

=========================================================================

*                          HDL Compilation                              *

=========================================================================

Compiling vhdl file "d:/mb-jpeg/synthesis/../hdl/system.vhd" in Library work.

Entity  compiled.

Entity  (Architecture ) compiled.

=========================================================================

*                            HDL Analysis                               *

=========================================================================

Analyzing Entity  (Architecture ).

WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1452: Generating a Black Box for component .

WARNING:Xst:766 - "d:/mb-jpeg/synthesis/../hdl/system.vhd" line 1458: Generating a Black Box for component .

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Entity  analyzed. Unit  generated.

=========================================================================

*                           HDL Synthesis                               *

=========================================================================

Synthesizing Unit .

    Related source file is "d:/mb-jpeg/synthesis/../hdl/system.vhd".

WARNING:Xst:646 - Signal > is assigned but never used.

WARNING:Xst:646 - Signal > is assigned but never used.

Unit  synthesized.

=========================================================================

*                       Advanced HDL Synthesis                          *

=========================================================================

Advanced RAM inference ...

Advanced multiplier inference ...

Advanced Registered AddSub inference ...

Dynamic shift register inference ...

=========================================================================

HDL Synthesis Report

Found no macro

=========================================================================

=========================================================================

*                         Low Level Synthesis                           *

=========================================================================

Loading device for application Rf_Device from file '2vp30.nph' in environment c:/Xilinx.

Optimizing unit  ...

Mapping all equations...

Building and optimizing final netlist ...

=========================================================================

*                            Final Report                               *

=========================================================================

Final Results

RTL Top Level Output File Name     : ../implementation/system.ngr

Top Level Output File Name         : ../implementation/system.ngc

Output Format                      : ngc

Optimization Goal                  : speed

Keep Hierarchy                     : no

Design Statistics

# IOs                              : 140

Cell Usage :

# BELS                             : 2

#      GND                         : 1

#      VCC                         : 1

# IO Buffers                       : 140

#      IBUF                        : 5

#      IBUFG                       : 1

#      IOBUF                       : 88

#      OBUF                        : 46

# Others                           : 16

#      clk90_inv_wrapper           : 1

#      dcm_0_wrapper               : 1

#      dcm_1_wrapper               : 1

#      ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper: 1

#      ddr_clk90_inv_wrapper       : 1

#      debug_module_wrapper        : 1

#      dlmb_cntlr_wrapper          : 1

#      dlmb_wrapper                : 1

#      ilmb_cntlr_wrapper          : 1

#      ilmb_wrapper                : 1

#      lmb_bram_wrapper            : 1

#      mb_opb_wrapper              : 1

#      microblaze_0_wrapper        : 1

#      rs232_uart_1_wrapper        : 1

#      sysace_compactflash_wrapper : 1

#      sysclk_inv_wrapper          : 1

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 2vp30ff896-7

 Number of bonded IOBs:                140  out of    556    25%

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

No clock signals found in this design

Timing Summary:

---------------

Speed Grade: -7

   Minimum period: No path found

   Minimum input arrival time before clock: No path found

   Maximum output required time after clock: No path found

   Maximum combinational path delay: 2.924ns

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default path analysis

  Total number of paths / destination ports: 1594 / 1506

-------------------------------------------------------------------------

Delay:               2.924ns (Levels of Logic = 1)

  Source:            ddr_256mb_32mx64_rank1_row13_col10_cl2_5:DDR_DQS_O<7> (PAD)

  Destination:       fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> (PAD)

  Data Path: ddr_256mb_32mx64_rank1_row13_col10_cl2_5:DDR_DQS_O<7> to fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7>

                                Gate     Net

    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

    ----------------------------------------  ------------

    ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper:DDR_DQS_O<7>    1   0.000   0.332  ddr_256mb_32mx64_rank1_row13_col10_cl2_5 (fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_O<7>)

     IOBUF:I->IO               2.592          iobuf_69 (fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7>)

    ----------------------------------------

    Total                      2.924ns (2.592ns logic, 0.332ns route)

                                       (88.7% logic, 11.3% route)

=========================================================================

CPU : 10.42 / 10.64 s | Elapsed : 10.00 / 10.00 s

-->

Total memory usage is 161848 kilobytes

Number of errors   :    0 (   0 filtered)

Number of warnings :  144 (   0 filtered)

Number of infos    :    0 (   0 filtered)

Copying Xilinx Implementation tool scripts..

*********************************************

Running Xilinx Implementation tools..

*********************************************

xflow -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt system.ngc

Release 7.1.02i - Xflow H.38

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc2vp30ff896-7 -implement fast_runtime.opt

system.ngc

.... Copying flowfile c:/Xilinx/xilinx/data/fpga.flw into working directory

D:/mb-jpeg/implementation

Using Flow File: D:/mb-jpeg/implementation/fpga.flw

Using Option File(s):

 D:/mb-jpeg/implementation/fast_runtime.opt

Creating Script File ...

#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm

D:/mb-jpeg/implementation/system.ngc -uc system.ucf system.ngd

#----------------------------------------------#

Release 7.1.02i - ngdbuild H.42

Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -p xc2vp30ff896-7 -nt timestamp -bm system.bmm -uc

system.ucf D:/mb-jpeg/implementation/system.ngc system.ngd

Reading NGO file 'D:/mb-jpeg/implementation/system.ngc' ...

Loading design module "D:/mb-jpeg/implementation/microblaze_0_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/mb_opb_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/debug_module_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/ilmb_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/dlmb_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/dlmb_cntlr_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/ilmb_cntlr_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/lmb_bram_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/rs232_uart_1_wrapper.ngc"...

Loading design module

"D:/mb-jpeg/implementation/sysace_compactflash_wrapper.ngc"...

Loading design module

"D:/mb-jpeg/implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ngc"

...

Loading design module "D:/mb-jpeg/implementation/sysclk_inv_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/clk90_inv_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/ddr_clk90_inv_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/dcm_0_wrapper.ngc"...

Loading design module "D:/mb-jpeg/implementation/dcm_1_wrapper.ngc"...

Applying constraints in "system.ucf" to the design...

Checking timing specifications ...

INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification

   "TS_sys_clk_pin", was traced into DCM instance "dcm_0/dcm_0/DCM_INST". The

   following new TNM groups and period specifications were generated at the DCM

   output(s):

   CLK0: TS_dcm_0_dcm_0_CLK0_BUF=PERIOD dcm_0_dcm_0_CLK0_BUF

TS_sys_clk_pin*1.000000 HIGH 50.000000%

   CLK90: TS_dcm_0_dcm_0_CLK90_BUF=PERIOD dcm_0_dcm_0_CLK90_BUF

TS_sys_clk_pin*1.000000 PHASE + 2.500000 nS HIGH 50.000000%

Processing BMM file ...

Checking expanded design ...

WARNING:NgdBuild:443 - SFF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I0/FD

   RE_I' has unconnected output pin

WARNING:NgdBuild:443 - SFF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I4/FD

   RE_I' has unconnected output pin

WARNING:NgdBuild:443 - SFF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I3/FD

   RE_I' has unconnected output pin

WARNING:NgdBuild:443 - SFF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I2/FD

   RE_I' has unconnected output pin

WARNING:NgdBuild:443 - SFF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_VAC_CALC/Counter_Bit_I1/FD

   RE_I' has unconnected output pin

WARNING:NgdBuild:443 - SFF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/MW_RD_WR_I/ADDR_SEL_SYNC_FIFO_I/I_ADDR_CNTR/I_UP_DWN_COUNTER

   /I_CARRY_OUT' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM0REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM1REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM2REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM3REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM4REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_

5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM5REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM6REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM7REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM8REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM9REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM10REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM11REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM12REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM13REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM14REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM15REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM16REG_SP/REG' has unconnected

   output p

in

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM17REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM18REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM19REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM20REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM21REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM22REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM23REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM24REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM25REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM26REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM27REG_SP/REG' has unconnected

   outp

ut pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM28REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM29REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM30REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM31REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM32REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp

   er_V2_ASYNCH_FIFO_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fi

   fo_v4_0/mem/distmem/dist_mem/DPRAM/DPRAM0/DPRAM33REG_SP/REG' has unconnected

   output pin

WARNING:NgdBuild:440 - FF primitive

   'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_

   cl2_5/DDR_CTRL_I/RDDATA_PATH_I/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapp