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-- Description : Testbench instantiates core, data memory and instruction memory,
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-- Description : Testbench instantiates core, data memory and instruction memory,
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-- together with a character device.
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-- together with a character device.
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY std;
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library std;
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USE std.textio.ALL;
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use std.textio.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY testbench IS
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entity testbench is
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END testbench;
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end testbench;
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ARCHITECTURE arch OF testbench IS
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architecture arch of testbench is
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SIGNAL dmem_o : dmem_out_type;
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signal dmem_o : dmem_out_type;
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SIGNAL imem_o : imem_out_type;
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signal imem_o : imem_out_type;
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SIGNAL dmem_i : dmem_in_type;
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signal dmem_i : dmem_in_type;
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SIGNAL imem_i : imem_in_type;
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signal imem_i : imem_in_type;
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SIGNAL sys_clk_i : std_logic := '0';
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signal sys_clk_i : std_logic := '0';
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SIGNAL sys_int_i : std_logic := '0';
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signal sys_int_i : std_logic := '0';
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SIGNAL sys_rst_i : std_logic := '0';
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signal sys_rst_i : std_logic := '0';
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SIGNAL sys_ena_i : std_logic := '1';
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signal sys_ena_i : std_logic := '1';
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CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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constant std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0) := X"FFFFFFC0";
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CONSTANT rom_size : integer := 16;
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constant rom_size : integer := 16;
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CONSTANT ram_size : integer := 16;
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constant ram_size : integer := 16;
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SIGNAL mem_enable : std_logic;
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signal mem_enable : std_logic;
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SIGNAL chr_enable : std_logic;
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signal chr_enable : std_logic;
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SIGNAL chr_read : std_logic;
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signal chr_read : std_logic;
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SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
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signal sel_o : std_logic_vector(3 downto 0);
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SIGNAL mem_dat : std_logic_vector(31 DOWNTO 0);
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signal mem_dat : std_logic_vector(31 downto 0);
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SIGNAL chr_dat : std_logic_vector(31 DOWNTO 0);
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signal chr_dat : std_logic_vector(31 downto 0);
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SIGNAL chr_cnt : integer := 0;
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signal chr_cnt : integer := 0;
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BEGIN
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BEGIN
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sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_clk_i <= not sys_clk_i after 10000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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sys_rst_i <= '1' after 0 ps, '0' after 150000 ps;
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sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
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sys_int_i <= '1' after 500000000 ps, '0' after 500040000 ps;
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dmem_i.ena_i <= sys_ena_i;
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dmem_i.ena_i <= sys_ena_i;
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sel_o <= dmem_o.sel_o WHEN dmem_o.we_o = '1' ELSE (OTHERS => '0');
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sel_o <= dmem_o.sel_o when dmem_o.we_o = '1' else (others => '0');
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mem_enable <= NOT sys_rst_i AND dmem_o.ena_o AND NOT compare(dmem_o.adr_o, std_out_adr);
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mem_enable <= not sys_rst_i and dmem_o.ena_o and not compare(dmem_o.adr_o, std_out_adr);
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chr_enable <= NOT sys_rst_i AND dmem_o.ena_o AND compare(dmem_o.adr_o, std_out_adr);
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chr_enable <= not sys_rst_i and dmem_o.ena_o and compare(dmem_o.adr_o, std_out_adr);
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dmem_i.dat_i <= chr_dat WHEN chr_read = '1' ELSE mem_dat;
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dmem_i.dat_i <= chr_dat when chr_read = '1' else mem_dat;
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-- Character device
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-- Character device
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stdio: PROCESS(sys_clk_i)
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stdio: process(sys_clk_i)
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VARIABLE s : line;
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variable s : line;
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VARIABLE byte : std_logic_vector(7 DOWNTO 0);
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variable byte : std_logic_vector(7 downto 0);
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VARIABLE char : character;
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variable char : character;
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BEGIN
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begin
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IF rising_edge(sys_clk_i) THEN
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if rising_edge(sys_clk_i) then
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IF chr_enable = '1' THEN
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if chr_enable = '1' then
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IF dmem_o.we_o = '1' THEN
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if dmem_o.we_o = '1' then
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-- WRITE STDOUT
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-- WRITE STDOUT
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CASE dmem_o.sel_o IS
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case dmem_o.sel_o is
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WHEN "0001" => byte := dmem_o.dat_o( 7 DOWNTO 0);
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when "0001" => byte := dmem_o.dat_o( 7 downto 0);
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WHEN "0010" => byte := dmem_o.dat_o(15 DOWNTO 8);
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when "0010" => byte := dmem_o.dat_o(15 downto 8);
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WHEN "0100" => byte := dmem_o.dat_o(23 DOWNTO 16);
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when "0100" => byte := dmem_o.dat_o(23 downto 16);
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WHEN "1000" => byte := dmem_o.dat_o(31 DOWNTO 24);
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when "1000" => byte := dmem_o.dat_o(31 downto 24);
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WHEN OTHERS => NULL;
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when others => null;
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END CASE;
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end case;
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char := character'val(my_conv_integer(byte));
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char := character'val(my_conv_integer(byte));
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IF byte = X"0D" THEN
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if byte = X"0D" then
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-- Ignore character 13
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-- Ignore character 13
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ELSIF byte = X"0A" THEN
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elsif byte = X"0A" then
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-- Writeline on character 10 (newline)
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-- Writeline on character 10 (newline)
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writeline(output, s);
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writeline(output, s);
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ELSE
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else
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-- Write to buffer
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-- Write to buffer
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write(s, char);
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write(s, char);
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END IF;
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end if;
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chr_read <= '0';
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chr_read <= '0';
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ELSE
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else
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chr_read <= '1';
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chr_read <= '1';
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IF chr_cnt = 0 THEN
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if chr_cnt = 0 then
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chr_cnt <= 1;
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chr_cnt <= 1;
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chr_dat <= X"4C4C4C4C";
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chr_dat <= X"4C4C4C4C";
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ELSIF chr_cnt = 1 THEN
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elsif chr_cnt = 1 then
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chr_cnt <= 2;
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chr_cnt <= 2;
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chr_dat <= X"4D4D4D4D";
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chr_dat <= X"4D4D4D4D";
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ELSIF chr_cnt = 2 THEN
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elsif chr_cnt = 2 then
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chr_cnt <= 3;
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chr_cnt <= 3;
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chr_dat <= X"4E4E4E4E";
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chr_dat <= X"4E4E4E4E";
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ELSIF chr_cnt = 3 THEN
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elsif chr_cnt = 3 then
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chr_cnt <= 0;
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chr_cnt <= 0;
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chr_dat <= X"0A0A0A0A";
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chr_dat <= X"0A0A0A0A";
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END IF;
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end if;
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END IF;
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end if;
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ELSE
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else
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chr_read <= '0';
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chr_read <= '0';
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS;
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end process;
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-- Warning: an infinite loop like while(1) {} triggers this timeout too!
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-- Warning: an infinite loop like while(1) {} triggers this timeout too!
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-- disable this feature when a premature finish occur.
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-- disable this feature when a premature finish occur.
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timeout: PROCESS(sys_clk_i)
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timeout: process(sys_clk_i)
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BEGIN
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begin
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IF NOW = 10 ms THEN
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if now = 10 ms then
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REPORT "TIMEOUT" SEVERITY FAILURE;
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report "TIMEOUT" severity FAILURE;
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END IF;
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end if;
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-- BREAK ON EXIT (0xB8000000)
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-- BREAK ON EXIT (0xB8000000)
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IF compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' THEN
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if compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' then
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-- Make sure the simulator finishes when an error is encountered.
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-- Make sure the simulator finishes when an error is encountered.
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-- For modelsim: see menu Simulate -> Runtime options -> Assertions
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-- For modelsim: see menu Simulate -> Runtime options -> Assertions
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REPORT "FINISHED" SEVERITY FAILURE;
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report "FINISHED" severity FAILURE;
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END IF;
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end if;
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END PROCESS;
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end process;
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imem : sram GENERIC MAP
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imem : sram generic map
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(
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(
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WIDTH => CFG_IMEM_WIDTH,
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WIDTH => CFG_IMEM_WIDTH,
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SIZE => rom_size - 2
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SIZE => rom_size - 2
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => imem_i.dat_i,
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dat_o => imem_i.dat_i,
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dat_i => "00000000000000000000000000000000",
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dat_i => "00000000000000000000000000000000",
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adr_i => imem_o.adr_o(rom_size - 1 DOWNTO 2),
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adr_i => imem_o.adr_o(rom_size - 1 downto 2),
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wre_i => '0',
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wre_i => '0',
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ena_i => imem_o.ena_o,
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ena_i => imem_o.ena_o,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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dmem : sram_4en GENERIC MAP
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dmem : sram_4en generic map
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(
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(
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WIDTH => CFG_DMEM_WIDTH,
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WIDTH => CFG_DMEM_WIDTH,
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SIZE => ram_size - 2
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SIZE => ram_size - 2
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => mem_dat,
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dat_o => mem_dat,
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dat_i => dmem_o.dat_o,
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dat_i => dmem_o.dat_o,
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adr_i => dmem_o.adr_o(ram_size - 1 DOWNTO 2),
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adr_i => dmem_o.adr_o(ram_size - 1 downto 2),
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wre_i => sel_o,
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wre_i => sel_o,
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ena_i => mem_enable,
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ena_i => mem_enable,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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core0 : core PORT MAP
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core0 : core port map
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(
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(
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imem_o => imem_o,
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imem_o => imem_o,
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dmem_o => dmem_o,
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dmem_o => dmem_o,
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imem_i => imem_i,
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imem_i => imem_i,
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dmem_i => dmem_i,
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dmem_i => dmem_i,
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int_i => sys_int_i,
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int_i => sys_int_i,
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rst_i => sys_rst_i,
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rst_i => sys_rst_i,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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END arch;
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end arch;
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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-- USE CONFIGURATIONS INSTEAD OF GENERICS TO IMPLEMENT - FOR EXAMPLE - DIFFERENT MEMORIES.
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-- USE CONFIGURATIONS INSTEAD OF GENERICS TO IMPLEMENT - FOR EXAMPLE - DIFFERENT MEMORIES.
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-- CONFIGURATIONS CAN HIERARCHICALLY INVOKE OTHER CONFIGURATIONS TO REDUCE THE SIZE OF THE
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-- CONFIGURATIONS CAN HIERARCHICALLY INVOKE OTHER CONFIGURATIONS TO REDUCE THE SIZE OF THE
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-- CONFIGURATION DECLARATION
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-- CONFIGURATION DECLARATION
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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CONFIGURATION tb_conf_example OF testbench IS
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configuration tb_conf_example of testbench is
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FOR arch
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for arch
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FOR ALL: sram_4en
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for all: sram_4en
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USE ENTITY mblite.sram_4en(arch);
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use entity mblite.sram_4en(arch);
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END FOR;
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end for;
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END FOR;
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end for;
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END tb_conf_example;
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end tb_conf_example;
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No newline at end of file
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No newline at end of file
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