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Line 28... |
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COMPONENT mblite_stdio IS PORT
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COMPONENT mblite_stdio IS PORT
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(
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(
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dmem_i : OUT dmem_in_type;
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dmem_i : OUT dmem_in_type;
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dmem_o : IN dmem_out_type;
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dmem_o : IN dmem_out_type;
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clk_i : IN std_ulogic
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clk_i : IN std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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SIGNAL dmem_o : dmem_out_type;
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SIGNAL dmem_o : dmem_out_type;
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SIGNAL dmem_i : dmem_in_type;
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SIGNAL dmem_i : dmem_in_type;
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SIGNAL imem_o : imem_out_type;
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SIGNAL imem_o : imem_out_type;
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SIGNAL imem_i : imem_in_type;
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SIGNAL imem_i : imem_in_type;
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SIGNAL s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
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SIGNAL s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
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SIGNAL s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
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SIGNAL s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
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SIGNAL sys_clk_i : std_ulogic := '0';
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SIGNAL sys_clk_i : std_logic := '0';
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SIGNAL sys_int_i : std_ulogic;
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SIGNAL sys_int_i : std_logic;
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SIGNAL sys_rst_i : std_ulogic;
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SIGNAL sys_rst_i : std_logic;
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CONSTANT rom_size : integer := 16;
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CONSTANT rom_size : integer := 16;
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CONSTANT ram_size : integer := 16;
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CONSTANT ram_size : integer := 16;
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SIGNAL sel_o : std_ulogic_vector(3 DOWNTO 0);
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SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
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SIGNAL ena_o : std_ulogic;
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SIGNAL ena_o : std_logic;
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BEGIN
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BEGIN
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sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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