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-- Description : Testbench instantiates data and instruction memories, core,
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-- Description : Testbench instantiates data and instruction memories, core,
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-- core address decoder, wishbone adapter and wishbone stdio
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-- core address decoder, wishbone adapter and wishbone stdio
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY testbench IS
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entity testbench is
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END testbench;
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end testbench;
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ARCHITECTURE arch OF testbench IS
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architecture arch of testbench is
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COMPONENT wb_stdio IS PORT
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component wb_stdio is port
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(
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(
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wb_o : OUT wb_slv_out_type;
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wb_o : out wb_slv_out_type;
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wb_i : IN wb_slv_in_type
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wb_i : in wb_slv_in_type
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);
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);
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END COMPONENT;
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end component;
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SIGNAL dmem_o : dmem_out_type;
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signal dmem_o : dmem_out_type;
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SIGNAL dmem_i : dmem_in_type;
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signal dmem_i : dmem_in_type;
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SIGNAL imem_o : imem_out_type;
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signal imem_o : imem_out_type;
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SIGNAL imem_i : imem_in_type;
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signal imem_i : imem_in_type;
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SIGNAL s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
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signal s_dmem_o : dmem_out_array_type(CFG_NUM_SLAVES - 1 downto 0);
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SIGNAL s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 DOWNTO 0);
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signal s_dmem_i : dmem_in_array_type(CFG_NUM_SLAVES - 1 downto 0);
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SIGNAL m_wb_i : wb_mst_in_type;
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signal m_wb_i : wb_mst_in_type;
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SIGNAL m_wb_o : wb_mst_out_type;
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signal m_wb_o : wb_mst_out_type;
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SIGNAL s_wb_i : wb_slv_in_type;
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signal s_wb_i : wb_slv_in_type;
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SIGNAL s_wb_o : wb_slv_out_type;
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signal s_wb_o : wb_slv_out_type;
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SIGNAL sys_clk_i : std_logic := '0';
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signal sys_clk_i : std_logic := '0';
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SIGNAL sys_int_i : std_logic;
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signal sys_int_i : std_logic;
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SIGNAL sys_rst_i : std_logic;
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signal sys_rst_i : std_logic;
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CONSTANT rom_size : integer := 16;
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constant rom_size : integer := 16;
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CONSTANT ram_size : integer := 16;
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constant ram_size : integer := 16;
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SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
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signal sel_o : std_logic_vector(3 downto 0);
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SIGNAL ena_o : std_logic;
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signal ena_o : std_logic;
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BEGIN
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begin
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sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_clk_i <= not sys_clk_i after 10000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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sys_rst_i <= '1' after 0 ps, '0' after 150000 ps;
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sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
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sys_int_i <= '1' after 500000000 ps, '0' after 500040000 ps;
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-- Warning: an infinite loop like while(1) {} triggers this timeout too!
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-- Warning: an infinite loop like while(1) {} triggers this timeout too!
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-- disable this feature when a premature finish occur.
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-- disable this feature when a premature finish occur.
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timeout: PROCESS(sys_clk_i)
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timeout: process(sys_clk_i)
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BEGIN
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begin
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IF NOW = 10 ms THEN
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if NOW = 10 ms then
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REPORT "TIMEOUT" SEVERITY FAILURE;
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report "TIMEOUT" severity FAILURE;
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END IF;
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end if;
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-- BREAK ON EXIT (0xB8000000)
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-- BREAK ON EXIT (0xB8000000)
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IF compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' THEN
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if compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' then
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-- Make sure the simulator finishes when an error is encountered.
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-- Make sure the simulator finishes when an error is encountered.
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-- For modelsim: see menu Simulate -> Runtime options -> Assertions
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-- For modelsim: see menu Simulate -> Runtime options -> Assertions
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REPORT "FINISHED" SEVERITY FAILURE;
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report "FINISHED" severity FAILURE;
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END IF;
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end if;
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END PROCESS;
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end process;
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s_wb_i.clk_i <= sys_clk_i;
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s_wb_i.clk_i <= sys_clk_i;
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s_wb_i.rst_i <= sys_rst_i;
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s_wb_i.rst_i <= sys_rst_i;
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s_wb_i.adr_i <= m_wb_o.adr_o;
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s_wb_i.adr_i <= m_wb_o.adr_o;
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s_wb_i.dat_i <= m_wb_o.dat_o;
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s_wb_i.dat_i <= m_wb_o.dat_o;
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Line 89... |
m_wb_i.rst_i <= sys_rst_i;
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m_wb_i.rst_i <= sys_rst_i;
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m_wb_i.dat_i <= s_wb_o.dat_o;
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m_wb_i.dat_i <= s_wb_o.dat_o;
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m_wb_i.ack_i <= s_wb_o.ack_o;
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m_wb_i.ack_i <= s_wb_o.ack_o;
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m_wb_i.int_i <= s_wb_o.int_o;
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m_wb_i.int_i <= s_wb_o.int_o;
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stdio : wb_stdio PORT MAP
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stdio : wb_stdio port map
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(
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(
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wb_i => s_wb_i,
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wb_i => s_wb_i,
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wb_o => s_wb_o
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wb_o => s_wb_o
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);
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);
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wb_adapter : core_wb_adapter PORT MAP
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wb_adapter : core_wb_adapter port map
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(
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(
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dmem_i => s_dmem_i(1),
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dmem_i => s_dmem_i(1),
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wb_o => m_wb_o,
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wb_o => m_wb_o,
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dmem_o => s_dmem_o(1),
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dmem_o => s_dmem_o(1),
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wb_i => m_wb_i
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wb_i => m_wb_i
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);
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);
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s_dmem_i(0).ena_i <= '1';
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s_dmem_i(0).ena_i <= '1';
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sel_o <= s_dmem_o(0).sel_o WHEN s_dmem_o(0).we_o = '1' ELSE (OTHERS => '0');
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sel_o <= s_dmem_o(0).sel_o when s_dmem_o(0).we_o = '1' else (others => '0');
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ena_o <= NOT sys_rst_i AND s_dmem_o(0).ena_o;
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ena_o <= not sys_rst_i and s_dmem_o(0).ena_o;
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dmem : sram_4en GENERIC MAP
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dmem : sram_4en generic map
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(
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(
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WIDTH => CFG_DMEM_WIDTH,
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WIDTH => CFG_DMEM_WIDTH,
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SIZE => ram_size - 2
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SIZE => ram_size - 2
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => s_dmem_i(0).dat_i,
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dat_o => s_dmem_i(0).dat_i,
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dat_i => s_dmem_o(0).dat_o,
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dat_i => s_dmem_o(0).dat_o,
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adr_i => s_dmem_o(0).adr_o(ram_size - 1 DOWNTO 2),
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adr_i => s_dmem_o(0).adr_o(ram_size - 1 downto 2),
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wre_i => sel_o,
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wre_i => sel_o,
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ena_i => ena_o,
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ena_i => ena_o,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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decoder : core_address_decoder GENERIC MAP
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decoder : core_address_decoder generic map
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(
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(
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G_NUM_SLAVES => CFG_NUM_SLAVES
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G_NUM_SLAVES => CFG_NUM_SLAVES
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)
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)
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PORT MAP
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port map
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(
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(
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m_dmem_i => dmem_i,
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m_dmem_i => dmem_i,
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s_dmem_o => s_dmem_o,
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s_dmem_o => s_dmem_o,
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m_dmem_o => dmem_o,
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m_dmem_o => dmem_o,
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s_dmem_i => s_dmem_i,
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s_dmem_i => s_dmem_i,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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imem : sram GENERIC MAP
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imem : sram generic map
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(
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(
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WIDTH => CFG_IMEM_WIDTH,
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WIDTH => CFG_IMEM_WIDTH,
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SIZE => rom_size - 2
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SIZE => rom_size - 2
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => imem_i.dat_i,
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dat_o => imem_i.dat_i,
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dat_i => "00000000000000000000000000000000",
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dat_i => "00000000000000000000000000000000",
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adr_i => imem_o.adr_o(rom_size - 1 DOWNTO 2),
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adr_i => imem_o.adr_o(rom_size - 1 downto 2),
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wre_i => '0',
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wre_i => '0',
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ena_i => imem_o.ena_o,
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ena_i => imem_o.ena_o,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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core0 : core PORT MAP
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core0 : core port map
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(
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(
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imem_o => imem_o,
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imem_o => imem_o,
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dmem_o => dmem_o,
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dmem_o => dmem_o,
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imem_i => imem_i,
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imem_i => imem_i,
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dmem_i => dmem_i,
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dmem_i => dmem_i,
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int_i => sys_int_i,
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int_i => sys_int_i,
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rst_i => sys_rst_i,
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rst_i => sys_rst_i,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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END arch;
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end arch;
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No newline at end of file
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No newline at end of file
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