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--
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--
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-- Description : Simulates standard output using stdio package
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-- Description : Simulates standard output using stdio package
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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USE std.textio.ALL;
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use std.textio.all;
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ENTITY wb_stdio IS PORT
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entity wb_stdio is port
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(
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(
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wb_o : OUT wb_slv_out_type;
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wb_o : out wb_slv_out_type;
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wb_i : IN wb_slv_in_type
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wb_i : in wb_slv_in_type
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);
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);
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END wb_stdio;
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end wb_stdio;
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ARCHITECTURE arch OF wb_stdio IS
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architecture arch of wb_stdio is
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CONSTANT ack_assert_delay : TIME := 2 ns;
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constant ack_assert_delay : TIME := 2 ns;
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CONSTANT ack_deassert_delay : TIME := 2 ns;
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constant ack_deassert_delay : TIME := 2 ns;
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SIGNAL ack : std_logic;
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signal ack : std_logic;
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SIGNAL chr_dat : std_logic_vector(31 DOWNTO 0);
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signal chr_dat : std_logic_vector(31 downto 0);
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SIGNAL chr_cnt : natural := 0;
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signal chr_cnt : natural := 0;
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BEGIN
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begin
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wb_o.int_o <= '0';
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wb_o.int_o <= '0';
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wb_o.dat_o <= chr_dat;
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wb_o.dat_o <= chr_dat;
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-- Character device
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-- Character device
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stdio: PROCESS(wb_i.clk_i)
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stdio: process(wb_i.clk_i)
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VARIABLE s : line;
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variable s : line;
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VARIABLE byte : std_logic_vector(7 DOWNTO 0);
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variable byte : std_logic_vector(7 downto 0);
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VARIABLE char : character;
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variable char : character;
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BEGIN
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begin
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IF rising_edge(wb_i.clk_i) THEN
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if rising_edge(wb_i.clk_i) then
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IF (wb_i.stb_i AND wb_i.cyc_i) = '1' THEN
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if (wb_i.stb_i and wb_i.cyc_i) = '1' then
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IF wb_i.we_i = '1' AND ack = '0' THEN
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if wb_i.we_i = '1' and ack = '0' then
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-- WRITE STDOUT
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-- WRITE STDOUT
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wb_o.ack_o <= '1' AFTER ack_assert_delay;
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wb_o.ack_o <= '1' after ack_assert_delay;
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ack <= '1';
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ack <= '1';
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CASE wb_i.sel_i IS
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case wb_i.sel_i is
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WHEN "0001" => byte := wb_i.dat_i( 7 DOWNTO 0);
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when "0001" => byte := wb_i.dat_i( 7 downto 0);
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WHEN "0010" => byte := wb_i.dat_i(15 DOWNTO 8);
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when "0010" => byte := wb_i.dat_i(15 downto 8);
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WHEN "0100" => byte := wb_i.dat_i(23 DOWNTO 16);
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when "0100" => byte := wb_i.dat_i(23 downto 16);
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WHEN "1000" => byte := wb_i.dat_i(31 DOWNTO 24);
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when "1000" => byte := wb_i.dat_i(31 downto 24);
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WHEN OTHERS => NULL;
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when others => null;
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END CASE;
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end case;
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char := character'val(my_conv_integer(byte));
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char := character'val(my_conv_integer(byte));
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IF byte = X"0D" THEN
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if byte = X"0D" then
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-- Ignore character 13
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-- Ignore character 13
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ELSIF byte = X"0A" THEN
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elsif byte = X"0A" then
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-- Writeline on character 10 (newline)
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-- Writeline on character 10 (newline)
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writeline(output, s);
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writeline(output, s);
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ELSE
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else
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-- Write to buffer
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-- Write to buffer
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write(s, char);
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write(s, char);
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END IF;
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end if;
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ELSIF ack = '0' THEN
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elsif ack = '0' then
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-- READ stdout
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-- READ stdout
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ack <= '1';
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ack <= '1';
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wb_o.ack_o <= '1' AFTER ack_assert_delay;
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wb_o.ack_o <= '1' after ack_assert_delay;
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IF chr_cnt = 0 THEN
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if chr_cnt = 0 then
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chr_cnt <= 1;
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chr_cnt <= 1;
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chr_dat <= X"4C4C4C4C";
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chr_dat <= X"4C4C4C4C";
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ELSIF chr_cnt = 1 THEN
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elsif chr_cnt = 1 then
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chr_cnt <= 2;
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chr_cnt <= 2;
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chr_dat <= X"4D4D4D4D";
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chr_dat <= X"4D4D4D4D";
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ELSIF chr_cnt = 2 THEN
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elsif chr_cnt = 2 then
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chr_cnt <= 3;
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chr_cnt <= 3;
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chr_dat <= X"4E4E4E4E";
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chr_dat <= X"4E4E4E4E";
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ELSIF chr_cnt = 3 THEN
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elsif chr_cnt = 3 then
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chr_cnt <= 0;
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chr_cnt <= 0;
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chr_dat <= X"0A0A0A0A";
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chr_dat <= X"0A0A0A0A";
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END IF;
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end if;
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END IF;
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end if;
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ELSE
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else
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ack <= '0';
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ack <= '0';
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wb_o.ack_o <= '0' AFTER ack_deassert_delay;
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END IF;
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END IF;
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END PROCESS;
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END arch;
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No newline at end of file
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wb_o.ack_o <= '0' after ack_deassert_delay;
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end if;
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end if;
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end process;
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end arch;
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No newline at end of file
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