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USE mblite.core_Pkg.ALL;
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USE mblite.core_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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|
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ENTITY mblite_soc IS PORT
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ENTITY mblite_soc IS PORT
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(
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(
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sys_clk_i : IN std_ulogic;
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sys_clk_i : IN std_logic;
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dbg_dmem_o_we_o : OUT std_ulogic;
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dbg_dmem_o_we_o : OUT std_logic;
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dbg_dmem_o_ena_o : OUT std_ulogic;
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dbg_dmem_o_ena_o : OUT std_logic;
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sys_rst_i : IN std_ulogic;
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sys_rst_i : IN std_logic;
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sys_ena_i : IN std_ulogic;
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sys_ena_i : IN std_logic;
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sys_int_i : IN std_ulogic;
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sys_int_i : IN std_logic;
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dbg_dmem_o_adr_o : OUT std_ulogic_vector (31 DOWNTO 0);
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dbg_dmem_o_adr_o : OUT std_logic_vector (31 DOWNTO 0);
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dbg_dmem_o_dat_o : OUT std_ulogic_vector (31 DOWNTO 0);
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dbg_dmem_o_dat_o : OUT std_logic_vector (31 DOWNTO 0);
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dbg_dmem_o_sel_o : OUT std_ulogic_vector ( 3 DOWNTO 0)
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dbg_dmem_o_sel_o : OUT std_logic_vector ( 3 DOWNTO 0)
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);
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);
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END mblite_soc;
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END mblite_soc;
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ARCHITECTURE arch OF mblite_soc IS
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ARCHITECTURE arch OF mblite_soc IS
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WIDTH : integer;
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WIDTH : integer;
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SIZE : integer
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SIZE : integer
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);
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);
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PORT
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PORT
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(
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(
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dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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wre_i : IN std_ulogic;
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wre_i : IN std_logic;
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ena_i : IN std_ulogic;
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ena_i : IN std_logic;
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clk_i : IN std_ulogic
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clk_i : IN std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT sram_4en_init IS GENERIC
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COMPONENT sram_4en_init IS GENERIC
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(
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(
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WIDTH : integer;
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WIDTH : integer;
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SIZE : integer
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SIZE : integer
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);
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);
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PORT
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PORT
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(
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(
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dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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wre_i : IN std_ulogic_vector(3 DOWNTO 0);
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wre_i : IN std_logic_vector(3 DOWNTO 0);
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ena_i : IN std_ulogic;
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ena_i : IN std_logic;
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clk_i : IN std_ulogic
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clk_i : IN std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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SIGNAL dmem_o : dmem_out_type;
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SIGNAL dmem_o : dmem_out_type;
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SIGNAL imem_o : imem_out_type;
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SIGNAL imem_o : imem_out_type;
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SIGNAL dmem_i : dmem_in_type;
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SIGNAL dmem_i : dmem_in_type;
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SIGNAL imem_i : imem_in_type;
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SIGNAL imem_i : imem_in_type;
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SIGNAL mem_enable : std_ulogic;
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SIGNAL mem_enable : std_logic;
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SIGNAL sel_o : std_ulogic_vector(3 DOWNTO 0);
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SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
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CONSTANT std_out_adr : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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CONSTANT rom_size : integer := 13;
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CONSTANT rom_size : integer := 13;
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CONSTANT ram_size : integer := 13;
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CONSTANT ram_size : integer := 13;
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BEGIN
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BEGIN
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