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--
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--
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-- Description : Instantiates instruction- and datamemories and the core
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-- Description : Instantiates instruction- and datamemories and the core
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY mblite_soc IS PORT
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entity mblite_soc is port
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(
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(
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sys_clk_i : IN std_logic;
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sys_clk_i : in std_logic;
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dbg_dmem_o_we_o : OUT std_logic;
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dbg_dmem_o_we_o : out std_logic;
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dbg_dmem_o_ena_o : OUT std_logic;
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dbg_dmem_o_ena_o : out std_logic;
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sys_rst_i : IN std_logic;
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sys_rst_i : in std_logic;
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sys_ena_i : IN std_logic;
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sys_ena_i : in std_logic;
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sys_int_i : IN std_logic;
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sys_int_i : in std_logic;
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dbg_dmem_o_adr_o : OUT std_logic_vector (31 DOWNTO 0);
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dbg_dmem_o_adr_o : out std_logic_vector (31 downto 0);
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dbg_dmem_o_dat_o : OUT std_logic_vector (31 DOWNTO 0);
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dbg_dmem_o_dat_o : out std_logic_vector (31 downto 0);
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dbg_dmem_o_sel_o : OUT std_logic_vector ( 3 DOWNTO 0)
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dbg_dmem_o_sel_o : out std_logic_vector ( 3 downto 0)
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);
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);
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END mblite_soc;
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end mblite_soc;
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ARCHITECTURE arch OF mblite_soc IS
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architecture arch of mblite_soc is
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COMPONENT sram_init IS GENERIC
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component sram_init is generic
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(
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(
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WIDTH : integer;
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WIDTH : integer;
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SIZE : integer
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SIZE : integer
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);
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);
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PORT
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port
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(
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(
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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adr_i : in std_logic_vector(SIZE - 1 downto 0);
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wre_i : IN std_logic;
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wre_i : in std_logic;
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ena_i : IN std_logic;
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ena_i : in std_logic;
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clk_i : IN std_logic
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clk_i : in std_logic
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);
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);
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END COMPONENT;
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end component;
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COMPONENT sram_4en_init IS GENERIC
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component sram_4en_init is generic
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(
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(
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WIDTH : integer;
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WIDTH : integer;
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SIZE : integer
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SIZE : integer
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);
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);
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PORT
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port
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(
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(
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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adr_i : in std_logic_vector(SIZE - 1 downto 0);
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wre_i : IN std_logic_vector(3 DOWNTO 0);
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wre_i : in std_logic_vector(3 downto 0);
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ena_i : IN std_logic;
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ena_i : in std_logic;
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clk_i : IN std_logic
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clk_i : in std_logic
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);
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);
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END COMPONENT;
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end component;
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SIGNAL dmem_o : dmem_out_type;
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signal dmem_o : dmem_out_type;
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SIGNAL imem_o : imem_out_type;
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signal imem_o : imem_out_type;
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SIGNAL dmem_i : dmem_in_type;
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signal dmem_i : dmem_in_type;
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SIGNAL imem_i : imem_in_type;
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signal imem_i : imem_in_type;
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SIGNAL mem_enable : std_logic;
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signal mem_enable : std_logic;
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SIGNAL sel_o : std_logic_vector(3 DOWNTO 0);
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signal sel_o : std_logic_vector(3 downto 0);
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CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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constant std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0) := X"FFFFFFC0";
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CONSTANT rom_size : integer := 13;
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constant rom_size : integer := 13;
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CONSTANT ram_size : integer := 13;
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constant ram_size : integer := 13;
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BEGIN
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begin
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dbg_dmem_o_we_o <= dmem_o.we_o;
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dbg_dmem_o_we_o <= dmem_o.we_o;
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dbg_dmem_o_ena_o <= dmem_o.ena_o;
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dbg_dmem_o_ena_o <= dmem_o.ena_o;
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dbg_dmem_o_adr_o <= dmem_o.adr_o;
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dbg_dmem_o_adr_o <= dmem_o.adr_o;
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dbg_dmem_o_dat_o <= dmem_o.dat_o;
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dbg_dmem_o_dat_o <= dmem_o.dat_o;
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dbg_dmem_o_sel_o <= dmem_o.sel_o;
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dbg_dmem_o_sel_o <= dmem_o.sel_o;
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imem : sram GENERIC MAP
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imem : sram generic map
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(
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(
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WIDTH => CFG_IMEM_WIDTH,
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WIDTH => CFG_IMEM_WIDTH,
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SIZE => rom_size - 2
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SIZE => rom_size - 2
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => imem_i.dat_i,
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dat_o => imem_i.dat_i,
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dat_i => "00000000000000000000000000000000",
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dat_i => "00000000000000000000000000000000",
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adr_i => imem_o.adr_o(rom_size - 1 DOWNTO 2),
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adr_i => imem_o.adr_o(rom_size - 1 downto 2),
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wre_i => '0',
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wre_i => '0',
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ena_i => imem_o.ena_o,
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ena_i => imem_o.ena_o,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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mem_enable <= NOT sys_rst_i AND dmem_o.ena_o AND NOT compare(dmem_o.adr_o, std_out_adr);
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mem_enable <= not sys_rst_i and dmem_o.ena_o and not compare(dmem_o.adr_o, std_out_adr);
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sel_o <= dmem_o.sel_o WHEN dmem_o.we_o = '1' ELSE (OTHERS => '0');
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sel_o <= dmem_o.sel_o when dmem_o.we_o = '1' else (others => '0');
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dmem : sram_4en GENERIC MAP
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dmem : sram_4en generic map
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(
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(
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WIDTH => CFG_DMEM_WIDTH,
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WIDTH => CFG_DMEM_WIDTH,
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SIZE => ram_size - 2
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SIZE => ram_size - 2
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => dmem_i.dat_i,
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dat_o => dmem_i.dat_i,
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dat_i => dmem_o.dat_o,
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dat_i => dmem_o.dat_o,
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adr_i => dmem_o.adr_o(ram_size - 1 DOWNTO 2),
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adr_i => dmem_o.adr_o(ram_size - 1 downto 2),
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wre_i => sel_o,
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wre_i => sel_o,
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ena_i => mem_enable,
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ena_i => mem_enable,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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dmem_i.ena_i <= sys_ena_i;
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dmem_i.ena_i <= sys_ena_i;
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core0 : core PORT MAP
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core0 : core port map
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(
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(
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imem_o => imem_o,
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imem_o => imem_o,
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dmem_o => dmem_o,
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dmem_o => dmem_o,
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imem_i => imem_i,
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imem_i => imem_i,
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dmem_i => dmem_i,
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dmem_i => dmem_i,
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int_i => sys_int_i,
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int_i => sys_int_i,
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rst_i => sys_rst_i,
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rst_i => sys_rst_i,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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END arch;
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No newline at end of file
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end arch;
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No newline at end of file
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