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--
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--
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-- Description : Single Port Synchronous Random Access Memory
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-- Description : Single Port Synchronous Random Access Memory
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY sram_init IS GENERIC
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entity sram_init is generic
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(
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(
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WIDTH : integer := 32;
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WIDTH : integer := 32;
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SIZE : integer := 11
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SIZE : integer := 11
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);
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);
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PORT
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port
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(
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(
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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adr_i : in std_logic_vector(SIZE - 1 downto 0);
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wre_i : IN std_logic;
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wre_i : in std_logic;
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ena_i : IN std_logic;
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ena_i : in std_logic;
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clk_i : IN std_logic
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clk_i : in std_logic
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);
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);
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END sram_init;
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end sram_init;
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ARCHITECTURE arch OF sram_init IS
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architecture arch of sram_init is
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TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
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type ram_type is array (0 to 2 ** SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
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SIGNAL ram : ram_type := (
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signal ram : ram_type := (
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X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
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X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
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X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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X"00000000",X"00000000",X"00000000",X"00000000",X"31A01028",X"30400F18",X"B0000000",X"30209038",
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X"00000000",X"00000000",X"00000000",X"00000000",X"31A01028",X"30400F18",X"B0000000",X"30209038",
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X"B9F400C0",X"80000000",X"B9F406E8",X"30A30000",X"B8000000",X"E0601028",X"3021FFE4",X"F9E10000",
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X"B9F400C0",X"80000000",X"B9F406E8",X"30A30000",X"B8000000",X"E0601028",X"3021FFE4",X"F9E10000",
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X"BC030014",X"B8000040",X"F8600F20",X"99FC2000",X"80000000",X"E8600F20",X"E8830000",X"BE24FFEC",
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X"BC030014",X"B8000040",X"F8600F20",X"99FC2000",X"80000000",X"E8600F20",X"E8830000",X"BE24FFEC",
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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
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X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
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BEGIN
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begin
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PROCESS(clk_i)
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process(clk_i)
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BEGIN
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begin
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IF rising_edge(clk_i) THEN
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if rising_edge(clk_i) then
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IF notx(adr_i) AND ena_i = '1' THEN
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if notx(adr_i) and ena_i = '1' then
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IF wre_i = '1' THEN
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if wre_i = '1' then
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ram(my_conv_integer(adr_i)) <= dat_i;
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ram(my_conv_integer(adr_i)) <= dat_i;
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END IF;
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end if;
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dat_o <= ram(my_conv_integer(adr_i));
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dat_o <= ram(my_conv_integer(adr_i));
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS;
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end process;
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END arch;
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end arch;
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No newline at end of file
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No newline at end of file
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